Patents by Inventor Kee Sup Kim
Kee Sup Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11403452Abstract: Techniques for providing improved semiconductor yield learning are discussed herein. Some embodiments may include a yield learning vehicle (YLV), including a communication fabric and a plurality of circuit blocks connected with the communication fabric. The plurality of circuit blocks may include circuit blocks having different design window sizes, and may be configured to support different phases of a yield learning ramp up process. The YLV may further include a yield learning controller configured to control circuit block testing, and bypasses configured to partially or fully replicate the behavior of improperly functioning or untested circuit blocks. Some embodiments may include techniques for software implementation of the YLV, such as by invoking a computer to receive data representative of a design of the YLV, and based on the data representative of the design of the integrated circuit, causing the computer to generate data representative of YLV.Type: GrantFiled: October 19, 2016Date of Patent: August 2, 2022Assignee: Synopsys, Inc.Inventor: Kee Sup Kim
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Publication number: 20170109470Abstract: Techniques for providing improved semiconductor yield learning are discussed herein. Some embodiments may include a yield learning vehicle (YLV), including a communication fabric and a plurality of circuit blocks connected with the communication fabric. The plurality of circuit blocks may include circuit blocks having different design window sizes, and may be configured to support different phases of a yield learning ramp up process. The YLV may further include a yield learning controller configured to control circuit block testing, and bypasses configured to partially or fully replicate the behavior of improperly functioning or untested circuit blocks. Some embodiments may include techniques for software implementation of the YLV, such as by invoking a computer to receive data representative of a design of the YLV, and based on the data representative of the design of the integrated circuit, causing the computer to generate data representative of YLV.Type: ApplicationFiled: October 19, 2016Publication date: April 20, 2017Inventor: Kee Sup Kim
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Patent number: 9524922Abstract: The integrated circuit includes first and second vias, a first buffer configured to receive a signal transmitted from the first via, a second buffer configured to receive a signal transmitted from the second via, a first detour circuit configured to receive a signal transmitted through the second buffer, a second detour circuit configured to receive a signal transmitted through the first buffer, a first selector configured to selectively output one of the signal transmitted from the first via and a signal transmitted through the first detour circuit, and a second selector configured to selectively output one of the signal transmitted from the second via and a signal transmitted through the second detour circuit. Each of the first and second buffers and the first and second detour circuits transmits a signal in only one direction.Type: GrantFiled: March 23, 2015Date of Patent: December 20, 2016Assignees: SAMSUNG ELECTRONICS CO., LTD., SNU R&DB FOUNDATIONInventors: Kyounghwan Lim, Hyoun Soo Park, Kee Sup Kim, Bonghyun Lee, Chul Rim, JungYun Choi, Taewhan Kim, Heechun Park
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Patent number: 9459680Abstract: A temperature control method of a semiconductor device is provided. The temperature control method includes detecting a temperature of the semiconductor device; activating a reverse body biasing operation in which a body bias voltage applied to a function block of the semiconductor device is regulated, when the detected temperature is greater than a first temperature level; and activating a thermal throttling operation in which at least one of a frequency of a driving clock provided to a function block of the semiconductor device and a driving voltage applied to the function block of the semiconductor device is regulated, when the detected temperature is greater than a second temperature level that is different than the first temperature level.Type: GrantFiled: July 23, 2013Date of Patent: October 4, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyungock Kim, Wook Kim, Jun Seomun, Chungki Oh, JaeHan Jeon, Kyungtae Do, JungYun Choi, Hyosig Won, Kee Sup Kim
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Publication number: 20150371926Abstract: The integrated circuit includes first and second vias, a first buffer configured to receive a signal transmitted from the first via, a second buffer configured to receive a signal transmitted from the second via, a first detour circuit configured to receive a signal transmitted through the second buffer, a second detour circuit configured to receive a signal transmitted through the first buffer, a first selector configured to selectively output one of the signal transmitted from the first via and a signal transmitted through the first detour circuit, and a second selector configured to selectively output one of the signal transmitted from the second via and a signal transmitted through the second detour circuit. Each of the first and second buffers and the first and second detour circuits transmits a signal in only one direction.Type: ApplicationFiled: March 23, 2015Publication date: December 24, 2015Applicant: SNU R&DB FoundationInventors: Kyounghwan LIM, Hyoun Soo PARK, Kee Sup KIM, Bonghyun LEE, Chul RIM, JungYun CHOI, Taewhan KIM, Heechun PARK
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Publication number: 20140032949Abstract: A temperature control method of a semiconductor device is provided. The temperature control method includes detecting a temperature of the semiconductor device; activating a reverse body biasing operation in which a body bias voltage applied to a function block of the semiconductor device is regulated, when the detected temperature is greater than a first temperature level; and activating a thermal throttling operation in which at least one of a frequency of a driving clock provided to a function block of the semiconductor device and a driving voltage applied to the function block of the semiconductor device is regulated, when the detected temperature is greater than a second temperature level that is different than the first temperature level.Type: ApplicationFiled: July 23, 2013Publication date: January 30, 2014Inventors: Hyungock KIM, Wook KIM, Jun SEOMUN, Chungki OH, JaeHan JEON, Kyungtae DO, JungYun CHOI, Hyosig WON, Kee Sup KIM
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Patent number: 8522188Abstract: In a method of designing a system-on-chip including a tapless standard cell to which body biasing is applied, a slow corner timing parameter is adjusted to increase a slow corner of an operating speed distribution for the system-on-chip by reflecting forward body biasing, and a fast corner timing parameter is adjusted to decrease a fast corner of the operating speed distribution for the system-on-chip by reflecting reverse body biasing. The system-on-chip including the tapless standard cell is implemented based on the adjusted slow corner timing parameter corresponding to the increased slow corner and the adjusted fast corner timing parameter corresponding to the decreased fast corner. The slow corner timing parameter corresponds to a lowest value of an operating speed design window of the system-on-chip, and, the fast corner timing parameter corresponds to a highest value of the operating speed design window of the system-on-chip.Type: GrantFiled: September 25, 2012Date of Patent: August 27, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-Ock Kim, Jae-Han Jeon, Jung-Yun Choi, Kee-Sup Kim, Hyo-Sig Won
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Publication number: 20130185692Abstract: In a method of designing a system-on-chip including a tapless standard cell to which body biasing is applied, a slow corner timing parameter is adjusted to increase a slow corner of an operating speed distribution for the system-on-chip by reflecting forward body biasing, and a fast corner timing parameter is adjusted to decrease a fast corner of the operating speed distribution for the system-on-chip by reflecting reverse body biasing. The system-on-chip including the tapless standard cell is implemented based on the adjusted slow corner timing parameter corresponding to the increased slow corner and the adjusted fast corner timing parameter corresponding to the decreased fast corner. The slow corner timing parameter corresponds to a lowest value of an operating speed design window of the system-on-chip, and, the fast corner timing parameter corresponds to a highest value of the operating speed design window of the system-on-chip.Type: ApplicationFiled: September 25, 2012Publication date: July 18, 2013Inventors: Hyung-Ock KIM, Jae-Han JEON, Jung-Yun CHOI, Kee-Sup KIM, Hyo-Sig WON
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Publication number: 20130086536Abstract: A method of constructing a standard cell library for double patterning lithography (DPL) includes dividing a standard cell into a first region determined not to have an interaction with an adjacent outer cell and a second region that is likely to have such an interaction, generating data representative of DPL patterns corresponding to the first and second regions, and generating a standard cell library made up of the data. The library is then accessed and used to form a DPL mask. The DPL mask can be used to form a pattern on a substrate made up of a layout of cells in which the pattern of the standard cell is duplicated at several locations in the layout.Type: ApplicationFiled: September 14, 2012Publication date: April 4, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: WOOK KIM, HYUNG OCK KIM, JUNG YUN CHOI, KEE SUP KIM, HYO SIG WON
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Patent number: 7818642Abstract: In one embodiment, the present invention includes first level matrices, each including m input terminals and n output terminals, each coupled to a processor core, and second level matrices each coupled to the n output terminals of one of the first level matrices, where each of the second level matrices has n input terminals and p output terminals, and the p output terminals of the second level matrices correspond to a compacted output from the multiple processor cores. Other embodiments are described and claimed.Type: GrantFiled: September 25, 2007Date of Patent: October 19, 2010Assignee: Intel CorporationInventors: Kee Sup Kim, Ming Zhang, Avi Kovacs
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Patent number: 7814383Abstract: Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrated circuit testing. The number of outputs applied to output pins or other connectors may be substantially decreased, resulting in cost savings.Type: GrantFiled: October 17, 2005Date of Patent: October 12, 2010Inventors: Subhasish Mitra, Kee Sup Kim
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Patent number: 7574640Abstract: A compactor has a reduced number of outputs and the ability to handle a higher number of errors and unknown logic values. The procedure for designing the matrix and the resulting compactor involves determining the number of unknown logic values that may be encountered and adding columns to the compactor matrix based on the number of errors. Basically, the number of possible combinations of scan in lines is determined. Then, additional columns are added for each possible combination of scan in lines. The number of columns that are added for each combination of scan in lines is equal to the number of errors plus one in one embodiment.Type: GrantFiled: September 5, 2003Date of Patent: August 11, 2009Assignee: Intel CorporationInventors: Subhasish Mitra, Kee Sup Kim
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Patent number: 7523371Abstract: In one embodiment, an apparatus is provide with a combinational logic circuit to generate a data input signal; a delay element, coupled to the combinational logic circuit, to provide a delayed data input signal in response to the data input signal. Additionally, the apparatus is provided with a system bistable circuit, coupled to the combinational logic circuit, to generate a system bistable signal in response to at least the data input signal; a shadow bistable circuit, coupled to the delay element, to generate a shadow bistable signal in response to at least the delayed data input signal. Further, the apparatus is provided with an output joining circuit, coupled to the system and the shadow bistable circuits, to provide a data output signal in response to the system and the shadow bistable signals.Type: GrantFiled: September 2, 2005Date of Patent: April 21, 2009Assignee: Intel CorporationInventors: Subhasish Mitra, Ming Zhang, Kee Sup Kim
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Publication number: 20090083599Abstract: In one embodiment, the present invention includes first level matrices, each including m input terminals and n output terminals, each coupled to a processor core, and second level matrices each coupled to the n output terminals of one of the first level matrices, where each of the second level matrices has n input terminals and p output terminals, and the p output terminals of the second level matrices correspond to a compacted output from the multiple processor cores. Other embodiments are described and claimed.Type: ApplicationFiled: September 25, 2007Publication date: March 26, 2009Inventors: Kee Sup Kim, Ming Zhang, Avi Kovacs
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Patent number: 7278074Abstract: In one embodiment, an apparatus includes a system circuit adapted to generate at a first output terminal a first output signal in response to a data input signal and at least one system clock signal; a shadow circuit adapted to generate at a second output terminal a second output signal in response the data input signal and the at least one system clock signal; and an output joining circuit coupled to at least the first output terminal and the second output terminal.Type: GrantFiled: January 26, 2005Date of Patent: October 2, 2007Assignee: Intel CorporationInventors: Subhasish Mitra, Ming Zhang, Tak M. Mak, Quan Shi, Kee Sup Kim
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Patent number: 7240260Abstract: In one embodiment, a method is provided. In the method of this embodiment, a stimulus signal set may be generated and supplied, as input, to first circuitry. Each respective stimulus signal in the stimulus signal set may be generated based at least in part upon a respective non-null subset of an input signal set. No two respective stimulus signals in the stimulus signal set may be generated based upon the same respective non-null subset of the input signal set. The stimulus signal set may include a respective number of stimulus signals that is greater than a respective number of input signals in the input signal set. Of course, many modifications, variations, and alternatives are possible without departing from the method of this embodiment.Type: GrantFiled: December 11, 2002Date of Patent: July 3, 2007Assignee: Intel CorporationInventors: Subhasish Mitra, Kee Sup Kim
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Patent number: 7185253Abstract: Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrated circuit testing. The number of outputs applied to output pins or other connectors may be substantially decreased, resulting in cost savings.Type: GrantFiled: March 27, 2002Date of Patent: February 27, 2007Assignee: Intel CorporationInventors: Subhasish Mitra, Kee Sup Kim
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Patent number: 6918074Abstract: A testing device uses an input signature register to conduct “at speed” testing of asynchronous circuit responses in an effort to determine the operability of a monitored circuit. Upon receiving an enable signal, the input signature register quickly measures, compresses, and transmits the tested circuit responses so that the responses can be compared with a set of anticipated responses to determine whether the circuit is functioning properly. The enabled input signature register, such as a MISR or a SISR, generates an output signature, which contains the compressed responses of the monitored circuit and helps the testing device analyze circuit performance.Type: GrantFiled: June 28, 2002Date of Patent: July 12, 2005Assignee: Intel CorporationInventors: Kee Sup Kim, Shyang-Tai Sean Su, Adarsh Kalliat, Ajith Prasad
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Publication number: 20040117703Abstract: In one embodiment, a method is provided. In the method of this embodiment, a stimulus signal set may be generated and supplied, as input, to first circuitry. Each respective stimulus signal in the stimulus signal set may be generated based at least in part upon a respective non-null subset of an input signal set. No two respective stimulus signals in the stimulus signal set may be generated based upon the same respective non-null subset of the input signal set. The stimulus signal set may include a respective number of stimulus signals that is greater than a respective number of input signals in the input signal set. Of course, many modifications, variations, and alternatives are possible without departing from the method of this embodiment.Type: ApplicationFiled: December 11, 2002Publication date: June 17, 2004Inventors: Subhasish Mitra, Kee Sup Kim
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Publication number: 20040003332Abstract: A testing device uses an input signature register to conduct “at speed” testing of asynchronous circuit responses in an effort to determine the operability of a monitored circuit. Upon receiving an enable signal, the input signature register quickly measures, compresses, and transmits the tested circuit responses so that the responses can be compared with a set of anticipated responses to determine whether the circuit is functioning properly. The enabled input signature register, such as a MISR or a SISR, generates an output signature, which contains the compressed responses of the monitored circuit and helps the testing device analyze circuit performance.Type: ApplicationFiled: June 28, 2002Publication date: January 1, 2004Inventors: Kee Sup Kim, Shyang-Tai Sean Su, Adarsh Kalliat, Ajith Prasad