Patents by Inventor Keh-Chiang Ku
Keh-Chiang Ku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120280109Abstract: Techniques for promoting conductivity in a substrate for a pixel array. In an embodiment, an isolation region and a dopant well are disposed within an epitaxial layer adjoining the substrate, where a portion of the dopant well is between the substrate and a portion of the isolation well. In another embodiment, a contact is further disposed within the epitaxial layer, where a portion of the isolation region surrounds a portion of the contact.Type: ApplicationFiled: May 5, 2011Publication date: November 8, 2012Applicant: OMNIVISION TECHNOLOGIES, INC.Inventors: Duli Mao, Hsin-Chih Tai, Vincent Venezia, Keh-Chiang Ku, Rongsheng Yang
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Patent number: 8258546Abstract: A semiconductor device includes a semiconductor substrate and a transistor formed in the substrate, the transistor having a gate stack that has an interfacial layer formed on the substrate, a high-k dielectric layer formed over the interfacial layer, a metal layer formed over the high-dielectric layer, a capping layer formed between the interfacial layer and high-k dielectric layer; and a doped layer formed on the metal layer, the doped layer including at least F.Type: GrantFiled: July 20, 2011Date of Patent: September 4, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Lung Hung, Yong-Tian Hou, Keh-Chiang Ku, Chien-Hao Huang
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Publication number: 20120175722Abstract: A backside illuminated imaging sensor with a seal ring support includes an epitaxial layer having an imaging array formed in a front side of the epitaxial layer. A metal stack is coupled to the front side of the epitaxial layer, wherein the metal stack includes a seal ring formed in an edge region of the imaging sensor. An opening is included that extends from the back side of the epitaxial layer to a metal pad of the seal ring to expose the metal pad. The seal ring support is disposed on the metal pad and within the opening to structurally support the seal ring.Type: ApplicationFiled: January 6, 2011Publication date: July 12, 2012Applicant: OMNIVISION TECHNOLOGIES, INC.Inventors: Hsin-Chih Tai, Vincent Venezia, Yin Qian, Duli Mao, Keh-Chiang Ku
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Patent number: 8212253Abstract: A semiconductor structure comprises a gate stack in a semiconductor substrate and a lightly doped source/drain (LDD) region in the semiconductor substrate. The LDD region is adjacent to a region underlying the gate stack. The LDD region comprises carbon and an n-type impurity, and the n-type impurity comprises phosphorus tetramer.Type: GrantFiled: September 8, 2011Date of Patent: July 3, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Feng Nieh, Keh-Chiang Ku, Nai-Han Cheng, Chi-Chun Chen, Li-Te S. Lin
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Publication number: 20120080765Abstract: A method of fabricating a backside-illuminated pixel. The method includes forming frontside components of the pixel on or in a front side of a substrate, the frontside components including a photosensitive region of a first polarity. The method further includes forming a pure dopant region of a second polarity on a back side of the substrate, applying a laser pulse to the backside of the substrate to melt the pure dopant region, and recrystallizing the pure dopant region to form a backside doped layer. Corresponding apparatus embodiments are disclosed and claimed.Type: ApplicationFiled: October 1, 2010Publication date: April 5, 2012Applicant: OMNIVISION TECHNOLOGIES, INC.Inventors: Keh-Chiang Ku, Chia-Ying Liu, Hsin-Chih Tai, Vincent Venezia
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Publication number: 20110316079Abstract: A semiconductor structure comprises a gate stack in a semiconductor substrate and a lightly doped source/drain (LDD) region in the semiconductor substrate. The LDD region is adjacent to a region underlying the gate stack. The LDD region comprises carbon and an n-type impurity, and the n-type impurity comprises phosphorus tetramer.Type: ApplicationFiled: September 8, 2011Publication date: December 29, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Feng Nieh, Keh-Chiang Ku, Nai-Han Cheng, Chi-Chun Chen, Li-Te S. Lin
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Patent number: 8071429Abstract: Embodiments of a method for separating dies from a wafer having first and second sides. The process embodiment includes masking the first side of the wafer, the mask including openings therein to expose parts of the first side substantially aligned with scribe lines of the wafer. The process embodiment also includes etching from the exposed parts of the first side of the wafer until an intermediate position between the first and second sides and sawing the remainder of the wafer, starting from the intermediate position until reaching the second surface.Type: GrantFiled: November 24, 2010Date of Patent: December 6, 2011Assignee: OmniVision Technologies, Inc.Inventors: Yin Qian, Hsin-Chih Tai, Duli Mao, Vincent Venezia, Wei Zheng, Keh-Chiang Ku, Howard E. Rhodes
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Patent number: 8058134Abstract: An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.Type: GrantFiled: November 13, 2009Date of Patent: November 15, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Ting Wang, Keh-Chiang Ku, Yu-Chang Lin, Nai-Han Cheng, Li-Ping Huang
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Publication number: 20110272766Abstract: A semiconductor device includes a semiconductor substrate and a transistor formed in the substrate, the transistor having a gate stack that has an interfacial layer formed on the substrate, a high-k dielectric layer formed over the interfacial layer, a metal layer formed over the high-dielectric layer, a capping layer formed between the interfacial layer and high-k dielectric layer; and a doped layer formed on the metal layer, the doped layer including at least F.Type: ApplicationFiled: July 20, 2011Publication date: November 10, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Lung Hung, Yong-Tian Hou, Keh-Chiang Ku, Chien-Hao Huang
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Patent number: 8039375Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; implanting carbon into the semiconductor substrate; and implanting an n-type impurity into the semiconductor substrate to form a lightly doped source/drain (LDD) region, wherein the n-type impurity comprises more than one phosphorous atom. The n-type impurity may include phosphorous dimer or phosphorous tetramer.Type: GrantFiled: May 21, 2007Date of Patent: October 18, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Feng Nieh, Keh-Chiang Ku, Nai-Han Cheng, Chi-Chun Chen, Li-Te S. Lin
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Patent number: 7994051Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a high-k dielectric layer over a semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, forming a semiconductor layer over the metal layer, performing an implantation process on the semiconductor layer, the implantation process using a species including F, and forming a gate structure from the plurality of layers including the high-k dielectric layer, capping layer, metal layer, and semiconductor layer.Type: GrantFiled: October 17, 2008Date of Patent: August 9, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Lung Hung, Yong-Tian Hou, Keh-Chiang Ku, Chien-Hao Huang
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Publication number: 20110169991Abstract: An image sensor pixel includes a substrate doped to have a first conductivity type. A first epitaxial layer is disposed over the substrate and doped to also have the first conductivity type. A transfer transistor gate is formed on the first epitaxial layer. An epitaxially grown photo-sensor region is disposed in the first epitaxial layer and has a second conductivity type. The epitaxially grown photo-sensor region includes an extension region that extends under a portion of the transfer transistor gate.Type: ApplicationFiled: January 8, 2010Publication date: July 14, 2011Applicant: OMNIVISION TECHNOLOGIES, INC.Inventors: Keh-Chiang Ku, Chia-Ying Liu, Hsin-Chih Tai, Vincent Venezia, Yin Qian, Duli Mao
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Publication number: 20100210086Abstract: An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.Type: ApplicationFiled: November 13, 2009Publication date: August 19, 2010Inventors: Li-Ting Wang, Keh-Chiang Ku, Yu-Chang Lin, Nai-Han Cheng, Li-Ping Huang
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Patent number: 7741699Abstract: A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the gate stack wherein the N+ S/D region comprises an n-type impurity, a pre-amorphized implantation (PAI) region in the semiconductor substrate wherein the PAI region comprises an end of range (EOR) region, and an interstitial blocker region in the semiconductor substrate wherein the interstitial blocker region has a depth greater than a depth of the LDD region but less than a depth of the EOR region.Type: GrantFiled: September 15, 2006Date of Patent: June 22, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Keh-Chiang Ku, Chun-Feng Nieh, Li-Ping Huang, Chih-Chiang Wang, Chien-Hao Chen, Hsun Chang, Li-Ting Wang, Tze-Liang Lee, Shih-Chang Chen
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Patent number: 7736968Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer over the semiconductor substrate; forming a gate electrode layer over the gate dielectric layer; doping carbon and nitrogen into the gate electrode layer; and, after the step of doping carbon and nitrogen, patterning the gate dielectric layer and the gate electrode layer to form a gate dielectric and a gate electrode, respectively.Type: GrantFiled: October 27, 2008Date of Patent: June 15, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Keh-Chiang Ku, Cheng-Lung Hung, Li-Ting Wang, Chien-Hao Chen, Chien-Hao Huang, Wenli Lin, Yu-Chang Lin
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Publication number: 20100105185Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer over the semiconductor substrate; forming a gate electrode layer over the gate dielectric layer; doping carbon and nitrogen into the gate electrode layer; and, after the step of doping carbon and nitrogen, patterning the gate dielectric layer and the gate electrode layer to form a gate dielectric and a gate electrode, respectively.Type: ApplicationFiled: October 27, 2008Publication date: April 29, 2010Inventors: Keh-Chiang Ku, Cheng-Lung Hung, Li-Ting Wang, Chien-Hao Chen, Chien-Hao Huang, Wenli Lin, Yu-Chang Lin
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Publication number: 20100096705Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a high-k dielectric layer over a semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, forming a semiconductor layer over the metal layer, performing an implantation process on the semiconductor layer, the implantation process using a species including F, and forming a gate structure from the plurality of layers including the high-k dielectric layer, capping layer, metal layer, and semiconductor layer.Type: ApplicationFiled: October 17, 2008Publication date: April 22, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Lung Hung, Yong-Tian Hou, Keh-Chiang Ku, Chien-Hao Huang
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Publication number: 20100013029Abstract: A device and a method for forming a metal silicide is presented. A device, which includes a gate region, a source region, and a drain region, is formed on a substrate. A metal is disposed on the substrate, followed by a first anneal, forming a metal silicide on at least one of the gate region, the source region, and the drain region. The unreacted metal is removed from the substrate. The metal silicide is implanted with atoms. The implant is followed by a super anneal of the substrate.Type: ApplicationFiled: July 18, 2008Publication date: January 21, 2010Inventors: Harry Chuang, Hung-Chih Tsai, Keh-Chiang Ku, Kong-Beng Thei, Mong Song Liang
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Patent number: 7504292Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, and epitaxially growing a lightly-doped source/drain (LDD) region adjacent the gate stack, wherein carbon is simultaneously doped into the LDD region.Type: GrantFiled: December 5, 2006Date of Patent: March 17, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Keh-Chiang Ku, Pang-Yen Tsai, Chun-Feng Nieh, Li-Ting Wang
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Patent number: 7494857Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode on the gate dielectric; forming a source/drain region adjacent the gate dielectric and the gate electrode; forming an absorption-capping layer over the source/drain region and the gate electrode; performing an activation by applying a high-energy light to the absorption-capping layer; and removing the absorption-capping layer.Type: GrantFiled: December 29, 2006Date of Patent: February 24, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hao Chen, Tze-Liang Lee, Shih-Chang Chen, Keh-Chiang Ku, Chun-Feng Nieh, Li-Ting Wang, Hsun Chang