Patents by Inventor Keh-Jeng Chang
Keh-Jeng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11367695Abstract: An interposer includes one or more capacitors to store charge to provide signals to an integrated circuit electrically connected to the interposer. First connectors to each capacitor are interspersed with second connectors to the capacitors and are spaced apart from adjacent second connectors. The one or more capacitors and the resistances associated with the conductive paths between each capacitor and a connector or another capacitor can be modeled.Type: GrantFiled: June 12, 2019Date of Patent: June 21, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fong-yuan Chang, Cheng-Hung Yeh, Hsiang-Ho Chang, Po-Hsiang Huang, Chin-Her Chien, Sheng-Hsiung Chen, Aftab Alam Khan, Keh-Jeng Chang, Chin-Chou Liu, Yi-Kan Cheng
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Patent number: 11335606Abstract: The present disclosure describes a method to form a stacked semiconductor device with power rails. The method includes forming the stacked semiconductor device on a first surface of a substrate. The stacked semiconductor device includes a first fin structure, an isolation structure on the first fin structure, and a second fin structure above the first fin structure and in contact with the isolation structure. The first fin structure includes a first source/drain (S/D) region, and the second fin structure includes a second S/D region. The method also includes etching a second surface of the substrate and a portion of the first S/D region or the second S/D region to form an opening. The second surface is opposite to the first surface. The method further includes forming a dielectric barrier in the opening and forming an S/D contact in the opening.Type: GrantFiled: August 19, 2020Date of Patent: May 17, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chansyun David Yang, Keh-Jeng Chang, Chan-Lon Yang
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Patent number: 11282711Abstract: The present disclosure describes methods and systems for plasma-assisted etching of a metal oxide. The method includes modifying a surface of the metal oxide with a first gas, removing a top portion of the metal oxide by a ligand exchange reaction, and cleaning the surface of the metal oxide with a second gas.Type: GrantFiled: July 31, 2020Date of Patent: March 22, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chansyun David Yang, Keh-Jeng Chang, Chan-Lon Yang
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Patent number: 11276604Abstract: The present disclosure describes methods and systems for radical-activated etching of a metal oxide. The system includes a chamber, a wafer holder configured to hold a wafer with a metal oxide disposed thereon, a first gas line fluidly connected to the chamber and configured to deliver a gas to the chamber, a plasma generator configured to generate a plasma from the gas, a grid system between the plasma generator and the wafer holder and configured to increase a kinetic energy of ions from the plasma, a neutralizer between the grid system and the wafer holder and configured to generate electrons and neutralize the ions to generate radicals, and a second gas line fluidly connected to the chamber and configured to deliver a precursor across the wafer. The radicals facilitate etching of the metal oxide by the precursor.Type: GrantFiled: October 27, 2020Date of Patent: March 15, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chansyun David Yang, Chan-Lon Yang, Keh-Jeng Chang, Perng-Fei Yuh
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Publication number: 20220059414Abstract: The present disclosure describes a method to form a stacked semiconductor device with power rails. The method includes forming the stacked semiconductor device on a first surface of a substrate. The stacked semiconductor device includes a first fin structure, an isolation structure on the first fin structure, and a second fin structure above the first fin structure and in contact with the isolation structure. The first fin structure includes a first source/drain (S/D) region, and the second fin structure includes a second S/D region. The method also includes etching a second surface of the substrate and a portion of the first S/D region or the second S/D region to form an opening. The second surface is opposite to the first surface. The method further includes forming a dielectric barrier in the opening and forming an S/D contact in the opening.Type: ApplicationFiled: August 19, 2020Publication date: February 24, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chansyun David YANG, Keh-Jeng Chang, Chan-Lon Yang
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Publication number: 20220035253Abstract: A method for generating an extreme ultraviolet (EUV) radiation includes simultaneously irradiating two or more target droplets with laser light in an EUV radiation source apparatus to produce EUV radiation and collecting and directing the EUV radiation produced from the two or more target droplet by an imaging mirror.Type: ApplicationFiled: October 18, 2021Publication date: February 3, 2022Inventors: Chansyun David YANG, Keh-Jeng CHANG, Chan-Lon YANG
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Publication number: 20220037163Abstract: The present disclosure describes methods and systems for plasma-assisted etching of a metal oxide. The method includes modifying a surface of the metal oxide with a first gas, removing a top portion of the metal oxide by a ligand exchange reaction, and cleaning the surface of the metal oxide with a second gas.Type: ApplicationFiled: July 31, 2020Publication date: February 3, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chansyun David YANG, Keh-Jeng Chang, Chan-Lon Yang
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Publication number: 20220028842Abstract: A semiconductor package includes a first package component comprising: a first semiconductor die; a first encapsulant around the first semiconductor die; and a first redistribution structure electrically connected to the semiconductor die. The semiconductor package further includes a second package component bonded to the first package component, wherein the second package component comprises a second semiconductor die; a heat spreader between the first semiconductor die and the second package component; and a second encapsulant between the first package component and the second package component, wherein the second encapsulant has a lower thermal conductivity than the heat spreader.Type: ApplicationFiled: January 25, 2021Publication date: January 27, 2022Inventors: Fong-yuan Chang, Po-Hsiang Huang, Lee-Chung Lu, Jyh Chwen Frank Lee, Yii-Chian Lu, Yu-Hao Chen, Keh-Jeng Chang
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Publication number: 20220013652Abstract: The present disclosure describes a method includes forming a fin structure including a fin base portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer on the fin base portion, a second semiconductor layer above the first semiconductor layer, and a sacrificial semiconductor layer between the first and second semiconductor layers. The method further includes replacing the sacrificial semiconductor layer with a negative capacitance (NC) layer and forming gate electrodes around the NC layer, the first semiconductor layer, and the second semiconductor layer. The NC layer includes an NC dielectric material.Type: ApplicationFiled: July 10, 2020Publication date: January 13, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chansyun David Yang, Chan-Lon Yang, Keh-Jeng Chang
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Publication number: 20210384323Abstract: The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.Type: ApplicationFiled: August 23, 2021Publication date: December 9, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chansyun David YANG, Keh-Jeng CHANG, Chan-Lon YANG
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Publication number: 20210376137Abstract: The present disclosure describes a semiconductor device includes a first fin structure, an isolation structure in contact with a top surface of the first fin structure, a substrate layer in contact with the isolation structure, an epitaxial layer in contact with the isolation structure and the substrate layer, and a second fin structure above the first fin structure and in contact with the epitaxial layer.Type: ApplicationFiled: May 28, 2020Publication date: December 2, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chansyun David YANG, Keh-Jeng Chang, Chan-Lon Yang
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Patent number: 11150559Abstract: A method for generating an extreme ultraviolet (EUV) radiation includes simultaneously irradiating two or more target droplets with laser light in an EUV radiation source apparatus to produce EUV radiation and collecting and directing the EUV radiation produced from the two or more target droplet by an imaging mirror.Type: GrantFiled: July 27, 2020Date of Patent: October 19, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chansyun David Yang, Keh-Jeng Chang, Chan-Lon Yang
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Patent number: 11114547Abstract: The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.Type: GrantFiled: September 17, 2019Date of Patent: September 7, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chansyun David Yang, Keh-Jeng Chang, Chan-Lon Yang
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Publication number: 20210200102Abstract: A method for generating an extreme ultraviolet (EUV) radiation includes simultaneously irradiating two or more target droplets with laser light in an EUV radiation source apparatus to produce EUV radiation and collecting and directing the EUV radiation produced from the two or more target droplet by an imaging mirror.Type: ApplicationFiled: July 27, 2020Publication date: July 1, 2021Inventors: Chansyun David YANG, Keh-Jeng CHANG, Chan-Lon YANG
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Publication number: 20210083074Abstract: The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.Type: ApplicationFiled: September 17, 2019Publication date: March 18, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chansyun David YANG, Keh-Jeng CHANG, Chan-Lon YANG
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Publication number: 20200043873Abstract: An interposer includes one or more capacitors to store charge to provide signals to an integrated circuit electrically connected to the interposer. First connectors to each capacitor are interspersed with second connectors to the capacitors and are spaced apart from adjacent second connectors. The one or more capacitors and the resistances associated with the conductive paths between each capacitor and a connector or another capacitor can be modeled.Type: ApplicationFiled: June 12, 2019Publication date: February 6, 2020Inventors: Fong-yuan CHANG, Cheng-Hung YEH, Hsiang-Ho CHANG, Po-Hsiang HUANG, Chin-Her CHIEN, Sheng-Hsiung CHEN, Aftab Alam KHAN, Keh-Jeng CHANG, Chin-Chou LIU, Yi-Kan CHENG
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Patent number: 8115500Abstract: Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.Type: GrantFiled: January 27, 2011Date of Patent: February 14, 2012Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Yih-Yuh Doong, Keh-Jeng Chang, Yuh-Jier Mii, Sally Liu, Lien Jung Hung, Victor Chih Yuan Chang
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Publication number: 20110168995Abstract: Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.Type: ApplicationFiled: January 27, 2011Publication date: July 14, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yih-Yuh Doong, Keh-Jeng Chang, Yuh-Jier Mii, Sally Liu, Lien Jung Hung, Victor Chih Yuan Chang
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Patent number: 7880494Abstract: Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.Type: GrantFiled: March 2, 2010Date of Patent: February 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yih-Yuh Doong, Keh-Jeng Chang, Yuh-Jier Mii, Sally Liu, Lien Jung Hung, Victor Chih Yuan Chang
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Patent number: 7772868Abstract: Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.Type: GrantFiled: December 28, 2007Date of Patent: August 10, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yih-Yuh Doong, Keh-Jeng Chang, Yuh-Jier Mii, Sally Liu, Lien Jung Hung, Victor Chih Yuan Chang