Patents by Inventor Kei Fujii

Kei Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8461570
    Abstract: A method for manufacturing a semiconductor device, by which a multiple quantum well structure having a large number of pairs can be efficiently grown while maintaining good crystalline quality, and the semiconductor device, are provided. The semiconductor device manufacturing method of the present invention includes a step of forming a multiple quantum well structure 3 having 50 or more pairs of group III-V compound semiconductor quantum wells. In the step of forming the multiple quantum well structure 3, the multiple quantum well structure is formed by metal-organic vapor phase epitaxy using only metal-organic sources (all metal-organic source MOVPE).
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: June 11, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kei Fujii, Takashi Ishizuka, Katsushi Akita, Youichi Nagai, Tatsuya Tanabe
  • Publication number: 20130099203
    Abstract: A photodetector and a method of manufacturing the photodetector are provided, in which variation in sensitivity is suppressed over the near-infrared region from the short wavelength side including 1.3 ?m to the long wavelength side. The photodetector includes, on an InP substrate, an absorption layer of a type II multiple quantum well structure comprising a repeated structure of a GaAsSb layer and an InGaAs layer, and has sensitivity in the near-infrared region including wavelengths of 1.3 ?m and 2.0 ?m. The ratio of the sensitivity at the wavelength of 1.3 ?m to the sensitivity at the wavelength of 2.0 ?m is not smaller than 0.5 but not larger than 1.6.
    Type: Application
    Filed: June 15, 2011
    Publication date: April 25, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Katsushi Akita, Takashi Ishizuka, Kei Fujii, Hideaki Nakahata, Youichi Nagai, Hiroshi Inada, Yasuhiro Iguchi
  • Publication number: 20130048838
    Abstract: A light-receiving element includes an InP substrate 1, a light-receiving layer 3 having an MQW and located on the InP substrate 1, a contact layer 5 located on the light-receiving layer 3, a p-type region 6 extending from a surface of the contact layer 5 to the light-receiving layer, and a p-side electrode 11 that forms an ohmic contact with the p-type region. The light-receiving element is characterized in that the MQW has a laminated structure including pairs of an InxGa1-xAs (0.38?x?0.68) layer and a GaAs1-ySby (0.25?y?0.73) layer, and in the GaAs1-ySby layer, the Sb content y in a portion on the InP substrate side is larger than the Sb content y in a portion on the opposite side.
    Type: Application
    Filed: December 3, 2010
    Publication date: February 28, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroki Mori, Yasuhiro Iguchi, Hiroshi Inada, Youichi Nagai, Kouhei Miura, Hideaki Nakahata, Katsushi Akita, Takashi Ishizuka, Kei Fujii
  • Publication number: 20130032780
    Abstract: A photodiode and the like capable of preventing the responsivity on the short wavelength side from deteriorating while totally improving the responsivity in a type II MQW structure, is provided. The photodiode is formed on a group III-V compound semiconductor substrate 1, and includes a pixel P. The photodiode includes an absorption layer 3 of a type II MQW structure, which is located on the substrate 1. The MQW structure includes fifty or more pairs of two different types of group III-V compound semiconductor layers 3a and 3b. The thickness of one of the two different types of group III-V compound semiconductor layers, which layer 3a has a higher potential of a valence band, is thinner than the thickness of the other layer 3b.
    Type: Application
    Filed: September 28, 2011
    Publication date: February 7, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kei Fujii, Takashi Ishizuka, Katsushi Akita, Yasuhiro Iguchi, Hiroshi Inada, Youichi Nagai
  • Publication number: 20120326122
    Abstract: Provided are an epitaxial wafer, a photodiode, and the like that include an antimony-containing layer and can be efficiently produced such that protruding surface defects causing a decrease in the yield can be reduced and impurity contamination causing degradation of the performance can be suppressed. The production method includes a step of growing an antimony (Sb)-containing layer on a substrate 1 by metal-organic vapor phase epitaxy using only metal-organic sources; and a step of growing, on the antimony-containing layer, an antimony-free layer including a window layer 5, wherein, from the growth of the antimony-containing layer to completion of the growth of the window layer, the growth is performed at a growth temperature of 425° C. or more and 525° C. or less.
    Type: Application
    Filed: October 3, 2011
    Publication date: December 27, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kei Fujii, Katsushi Akita, Takashi Ishizuka
  • Publication number: 20120298957
    Abstract: The present invention provides a light receiving element array etc., having a high light-reception sensitivity in the near-infrared region, an optical sensor device, and a method for producing the light receiving element array. A light receiving element array 55 includes an n-type buffer layer 2 disposed on an InP substrate 1, an absorption layer 3 having a type-II MQW, a contact layer 5 disposed on the absorption layer, and a p-type region extending to the n-type buffer layer 2 through the absorption layer 3, wherein the p-type region formed by selective diffusion is separated from the p-type region of an adjacent light receiving element by a region that is not subjected to selective diffusion, and, in the n-type buffer layer, a p-n junction 15 is formed on a crossed face of a p-type carrier concentration of the p-type region and an n-type carrier concentration of the buffer layer.
    Type: Application
    Filed: March 10, 2011
    Publication date: November 29, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Yasuhiro Iguchi, Hiroshi Inada, Youichi Nagai, Hideaki Nakahata, Katsushi Akita, Takashi Ishizuka, Kei Fujii
  • Patent number: 8309380
    Abstract: Provided are a photodiode array and its manufacturing method, which maintain the crystalline quality of an absorption layer formed on a group III-V semiconductor substrate to obtain excellent characteristics, and which improve the crystallinity at the surface of a window layer; an epitaxial wafer used for manufacturing the photodiode array; and a method for manufacturing the epitaxial wafer. A method for manufacturing a photodiode array 1 having a plurality of absorption regions 21, includes the steps of: growing an absorption layer 7 on an n-type InP substrate 3; growing an InP window layer on the absorption layer 7; and diffusing a p-type impurity in regions, in the window layer 11, corresponding to the plurality of absorption regions 21. The window layer 11 is grown by MOVPE using only metal-organic sources, at a growth temperature equal to or lower than that of the absorption layer 7.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: November 13, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Katsushi Akita, Takashi Ishizuka, Kei Fujii, Youichi Nagai, Hideaki Nakahata
  • Publication number: 20120217478
    Abstract: Provided are a semiconductor device and an optical sensor device, each having reduced dark current, and detectivity extended toward longer wavelengths in the near-infrared. Further, a method for manufacturing the semiconductor device is provided. The semiconductor device 50 includes an absorption layer 3 of a type II (GaAsSb/InGaAs) MQW structure located on an InP substrate 1, and an InP contact layer 5 located on the MQW structure. In the MQW structure, a composition x (%) of GaAsSb is not smaller than 44%, a thickness z (nm) thereof is not smaller than 3 nm, and z??0.4x+24.6 is satisfied.
    Type: Application
    Filed: May 19, 2011
    Publication date: August 30, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Kei Fujii, Katsushi Akita, Takashi Ishizuka, Hideaki Nakahata, Yasuhiro Iguchi, Hiroshi Inada, Youichi Nagai
  • Patent number: 8252372
    Abstract: A sprayed film forming method and apparatus in which the thickness of the sprayed film in a predetermined region is increased so as to unify the entire thickness. A sprayed film is formed at a cylinder bore inner surface while a spraying gun is moved in an axial direction during rotation inside the bore. Air inside the bore is sucked out to prevent foreign material from being caught in the sprayed film. The flow rate inside the bore tends to become higher at an axial end on a suction side, resulting in a thinned region. The supply speed of a wire serving as a spraying material to the spraying gun or the number of sprays in this region is higher than those at other portions. The thickness at the axial end of the bore is made equal while suppressing an increase in working time and spraying material used.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: August 28, 2012
    Assignee: Nissan Motor Co. Ltd.
    Inventors: Daisuke Terada, Kiyohisa Suzuki, Eiji Shiotani, Akira Shimizu, Akiharu Tashiro, Kei Fujii
  • Publication number: 20120196398
    Abstract: Provided are a photodiode array and its manufacturing method, which maintain the crystalline quality of an absorption layer formed on a group III-V semiconductor substrate to obtain excellent characteristics, and which improve the crystallinity at the surface of a window layer; an epitaxial wafer used for manufacturing the photodiode array; and a method for manufacturing the epitaxial wafer. A method for manufacturing a photodiode array 1 having a plurality of absorption regions 21, includes the steps of: growing an absorption layer 7 on an n-type InP substrate 3; growing an InP window layer on the absorption layer 7; and diffusing a p-type impurity in regions, in the window layer 11, corresponding to the plurality of absorption regions 21. The window layer 11 is grown by MOVPE using only metal-organic sources, at a growth temperature equal to or lower than that of the absorption layer 7.
    Type: Application
    Filed: April 13, 2012
    Publication date: August 2, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Katsushi AKITA, Takashi ISHIZUKA, Kei FUJII, Youichi NAGAI, Hideaki NAKAHATA
  • Publication number: 20120168720
    Abstract: An object of the present invention is to provide a group III-V compound semiconductor photo detector comprising an absorption layer having a group III-V compound semiconductor layer containing Sb as a group V constituent element, and an n-type InP window layer, resulting in reduced dark current. The InP layer 23 grown on the absorption layer 23 contains antimony as impurity, due to the memory effect with antimony which is supplied during the growth of a GaAsSb layer of the absorption layer 21. In the group III-V compound semiconductor photo detector 11, the InP layer 23 contains antimony as impurity and is doped with silicon as n-type dopant. Although antimony impurities in the InP layer 23 generate holes, the silicon contained in the InP layer 23 compensates for the generated carriers. As a result, the second portion 23d of the InP layer 23 has sufficient n-type conductivity.
    Type: Application
    Filed: July 21, 2010
    Publication date: July 5, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Katsushi Akita, Takashi Ishizuka, Kei Fujii, Youichi Nagai
  • Patent number: 8198623
    Abstract: Provided are a photodiode array and its manufacturing method, which maintain the crystalline quality of an absorption layer formed on a group III-V semiconductor substrate to obtain excellent characteristics, and which improve the crystallinity at the surface of a window layer; an epitaxial wafer used for manufacturing the photodiode array; and a method for manufacturing the epitaxial wafer. A method for manufacturing a photodiode array 1 having a plurality of absorption regions 21, includes the steps of: growing an absorption layer 7 on an n-type InP substrate 3; growing an InP window layer on the absorption layer 7; and diffusing a p-type impurity in regions, in the window layer 11, corresponding to the plurality of absorption regions 21. The window layer 11 is grown by MOVPE using only metal-organic sources, at a growth temperature equal to or lower than that of the absorption layer 7.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: June 12, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Katsushi Akita, Takashi Ishizuka, Kei Fujii, Youichi Nagai, Hideaki Nakahata
  • Publication number: 20120008660
    Abstract: Provided is a III-nitride semiconductor laser allowing for provision of a low threshold with use of a semipolar plane. A primary surface 13a of a semiconductor substrate 13 is inclined at an angle of inclination AOFF in the range of not less than 50 degrees and not more than 70 degrees toward the a-axis direction of GaN with respect to a reference plane perpendicular to a reference axis Cx along the c-axis direction of GaN. A first cladding layer 15, an active layer 17, and a second cladding layer 19 are provided on the primary surface 13a of the semiconductor substrate 13. The well layers 23a of the active layer 17 comprise InGaN. A polarization degree P in the LED mode of emission from the active layer of the semiconductor laser that reaches lasing is not less than ?1 and not more than 0.1.
    Type: Application
    Filed: August 17, 2011
    Publication date: January 12, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kei FUJII, Masaki UENO, Katsushi AKITA, Takashi KYONO, Yusuke YOSHIZUMI, Takamichi SUMITOMO, Yohei ENYA
  • Publication number: 20110210313
    Abstract: A method for manufacturing a semiconductor device, by which a multiple quantum well structure having a large number of pairs can be efficiently grown while maintaining good crystalline quality, and the semiconductor device, are provided. The semiconductor device manufacturing method of the present invention includes a step of forming a multiple quantum well structure 3 having 50 or more pairs of group III-V compound semiconductor quantum wells. In the step of forming the multiple quantum well structure 3, the multiple quantum well structure is formed by metal-organic vapor phase epitaxy using only metal-organic sources (all metal-organic source MOVPE).
    Type: Application
    Filed: July 7, 2010
    Publication date: September 1, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kei Fujii, Takashi Ishizuka, Katsushi Akita, Youichi Nagai, Tatsuya Tanabe
  • Publication number: 20110101306
    Abstract: Provided are a photodiode array and its manufacturing method, which maintain the crystalline quality of an absorption layer formed on a group III-V semiconductor substrate to obtain excellent characteristics, and which improve the crystallinity at the surface of a window layer; an epitaxial wafer used for manufacturing the photodiode array; and a method for manufacturing the epitaxial wafer. A method for manufacturing a photodiode array 1 having a plurality of absorption regions 21, includes the steps of: growing an absorption layer 7 on an n-type InP substrate 3; growing an InP window layer on the absorption layer 7; and diffusing a p-type impurity in regions, in the window layer 11, corresponding to the plurality of absorption regions 21. The window layer 11 is grown by MOVPE using only metal-organic sources, at a growth temperature equal to or lower than that of the absorption layer 7.
    Type: Application
    Filed: October 29, 2010
    Publication date: May 5, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Katsushi AKITA, Takashi ISHIZUKA, Kei FUJII, Youichi NAGAI, Hideaki NAKAHATA
  • Patent number: 7874893
    Abstract: A honing method and honing control device suitable for the honing having a large processing area is provided. The honing control device includes a grinder and an expansion member for disposition in a processing hole of a workpiece. The amount of an expanding movement when the grinder contacts the inner surface of a gauge hole via the expansion member is stored as a target expansion amount by inserting a honing head into the gauge hole having the same size as a target processing diameter of a master gauge. Then, a honing of an inner surface of the processing hole is performed by inserting the honing head within a processing hole of a workpiece moving the grinder towards an outer side of a diametrical direction by the expansion member installed within the honing head to rotate the honing head. The honing is completed when the amount of the expanding movement of the grinder reaches a target expansion amount established by the master gauge.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: January 25, 2011
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Akiharu Tashiro, Takayuki Monchujo, Kiyohisa Suzuki, Jun Inomata, Ryuji Fukada, Eiji Shiotani, Daisuke Terada, Kei Fujii
  • Publication number: 20090104348
    Abstract: A sprayed film forming method and apparatus in which the thickness of the sprayed film in a predetermined region is increased so as to unify the entire thickness. A sprayed film is formed at a cylinder bore inner surface while a spraying gun is moved in an axial direction during rotation inside the bore. Air inside the bore is sucked out to prevent foreign material from being caught in the sprayed film. The flow rate inside the bore tends to become higher at an axial end on a suction side, resulting in a thinned region. The supply speed of a wire serving as a spraying material to the spraying gun or the number of sprays in this region is higher than those at other portions. The thickness at the axial end of the bore is made equal while suppressing an increase in working time and spraying material used.
    Type: Application
    Filed: October 22, 2008
    Publication date: April 23, 2009
    Applicant: NISSAN MOTOR CO., LTD.
    Inventors: Daisuke Terada, Kiyohisa Suzuki, Eiji Shiotani, Akira Shimizu, Akiharu Tashiro, Kei Fujii
  • Publication number: 20080305716
    Abstract: A honing method and honing control device suitable for the honing having a large processing area is provided. The honing control device includes a grinder and an expansion member for disposition in a processing hole of a workpiece. The amount of an expanding movement when the grinder contacts the inner surface of a gauge hole via the expansion member is stored as a target expansion amount by inserting a honing head into the gauge hole having the same size as a target processing diameter of a master gauge. Then, a honing of an inner surface of the processing hole is performed by inserting the honing head within a processing hole of a workpiece moving the grinder towards an outer side of a diametrical direction by the expansion member installed within the honing head to rotate the honing head. The honing is completed when the amount of the expanding movement of the grinder reaches a target expansion amount established by the master gauge.
    Type: Application
    Filed: June 5, 2008
    Publication date: December 11, 2008
    Applicant: Nissan Motor Co., Ltd.
    Inventors: Akiharu Tashiro, Takayuki Monchujo, Kiyohisa Suzuki, Jun Inomata, Ryuji Fukada, Eiji Shiotani, Daisuke Terada, Kei Fujii
  • Patent number: 7052401
    Abstract: A seal 5 free from a core bar is fitted on each of a vertical shaft 1v and a horizontal shaft 1h of a cross shaft 1. Bases 5c of adjoining seals 5 are pressed against each other in back-to-back contact.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: May 30, 2006
    Assignee: Koyo Seiko Co., Ltd.
    Inventors: Kouichirou Mizuno, Kei Fujii
  • Publication number: 20040166947
    Abstract: A seal 5 free from a core bar is fitted on each of a vertical shaft 1v and a horizontal shaft 1h of a cross shaft 1. Bases 5c of adjoining seals 5 are pressed against each other in back-to-back contact.
    Type: Application
    Filed: November 13, 2003
    Publication date: August 26, 2004
    Inventors: Kouichirou Mizuno, Kei Fujii