Patents by Inventor Kei Kanemoto
Kei Kanemoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7938506Abstract: In a method for manufacturing an inkjet recording head which includes a pressure generation chamber supplied with ink fluid and a nozzle opening leading to the pressure generation chamber, the method includes: (a) forming a first trench which serves as the pressure generation chamber on a first surface of a first substrate; (b) forming a second trench which serves as the nozzle opening on a bottom surface of the first trench; (c) forming a sacrificial film on the first trench and the second trench; (d) forming a diaphragm on the sacrificial film as well as on the first surface of the first substrate; (e) forming a piezoelectric element on the diaphragm; (f) grinding a second surface of the first substrate so as to open a bottom surface of the second trench; (g) forming an opening which exposes the sacrificial film on the first surface of the first substrate; and (h) removing the sacrificial film through the opening.Type: GrantFiled: March 6, 2009Date of Patent: May 10, 2011Assignee: Seiko Epson CorporationInventor: Kei Kanemoto
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PHYSICAL QUANTITY SENSOR, MANUFACTURING METHOD OF PHYSICAL QUANTITY SENSOR, AND ELECTRONIC APPARATUS
Publication number: 20110056296Abstract: A physical quantity sensor includes: a fixing part; an elastic deforming part; a movable weight part coupled to the fixing part via the elastic deforming part; a fixed arm part extended from the fixing part; and a movable arm part extended from the movable weight part and provided to face the fixed arm part via a gap, wherein the fixed arm part and the movable arm part are laminated structures containing insulating layers and conductor layers, the fixed arm part has a first side surface conductor film provided on a side surface of the fixed arm part and a first connecting electrode part using the conductor layer and electrically connected to the first side surface conductor film, and the movable arm part has a second side surface conductor film provided on aside surface opposed to the first side surface conductor film and a second connecting electrode part using the conductor layer and electrically connected to the second side surface conductor film.Type: ApplicationFiled: September 1, 2010Publication date: March 10, 2011Applicant: SEIKO EPSON CORPORATIONInventor: Kei KANEMOTO -
Publication number: 20110049653Abstract: An MEMS sensor includes: a fixation frame section; a movable weight section coupled to the fixation frame section via an elastically deformable section; a fixed electrode section extending from the fixation frame section toward the movable weight section; a movable electrode section extending from the movable weight section toward the fixation frame section, and disposed so as to be opposed to the fixed electrode section via a gap; a capacitance section composed mainly of the fixed electrode section and the movable electrode section; and an active element provided to the movable weight section.Type: ApplicationFiled: August 25, 2010Publication date: March 3, 2011Applicant: SEIKO EPSON CORPORATIONInventor: Kei KANEMOTO
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Publication number: 20100244160Abstract: A MEMS sensor formed by processing a multi-layer wiring structure, includes: a movable weight portion coupled to a fixed frame portion with an elastic deformable portion and having a hollow portion formed at the periphery; a capacitance electrode portion including a fixed electrode portion fixed to the fixed frame portion and a movable electrode portion connected to the movable weight portion and arranged to face the fixed electrode portion; and an adjusting layer for adjusting at least one of amass of the movable weight portion, a damping coefficient of the movable electrode portion, and spring characteristics in the elastic deformable portion, wherein the adjusting layer includes at least one insulating layer that is a constituent element of the multi-layer wiring structure.Type: ApplicationFiled: March 25, 2010Publication date: September 30, 2010Applicant: SEIKO EPSON CORPORATIONInventor: Kei KANEMOTO
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Publication number: 20100242606Abstract: A MEMS sensor manufactured by processing a multi-layer stacked structure formed on a substrate, includes: a fixed frame portion formed in the substrate; a movable weight portion coupled to the fixed frame portion via an elastic deformable portion and having a hollow portion formed at the periphery; a fixed electrode portion protrudingly formed from the fixed frame portion toward the hollow portion; and a movable electrode portion moving integrally with the movable weight portion and facing the fixed electrode portion, wherein the movable weight portion includes a first movable weight portion formed of the multi-layer stacked structure and a second movable weight portion positioned below the first movable weight portion and formed of the material of the substrate.Type: ApplicationFiled: March 25, 2010Publication date: September 30, 2010Applicant: Seiko Epson CorporationInventor: Kei KANEMOTO
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Patent number: 7625784Abstract: The disclosure includes methods of manufacturing a semiconductor device formed on an SOI structure. In one example, a first and second semiconductor layer is formed on a semiconductor substrate including a first region. The first semiconductor layer and the second semiconductor layer are removed from a second region to form a recess for a support. A support precursor layer is formed. A portion of the support precursor layer is removed to form a support coupling the recess and the second semiconductor layer. A part of the first and second semiconductor layer is etched using the support as a mask. The first semiconductor layer is etched and removed to form a cavity under the second semiconductor layer. The second semiconductor layer is thermally oxidized to form a buried insulating layer in the cavity and the support is removed from at least the first region to expose the second semiconductor layer.Type: GrantFiled: June 19, 2007Date of Patent: December 1, 2009Assignee: Seiko Epson CorporationInventor: Kei Kanemoto
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Patent number: 7622359Abstract: A method for manufacturing a semiconductor device, includes: (a) forming a SiGe layer on a Si substrate; (b) forming a Si layer on the SiGe layer; (c) forming a dummy pattern made of SiGe in a dummy region of the Si substrate; and (d) wet-etching and removing the SiGe layer formed under the Si layer. In the step (d), an etchant is kept to contact the dummy pattern from before a complete remove of the SiGe layer to an end of the etching.Type: GrantFiled: February 4, 2008Date of Patent: November 24, 2009Assignee: Seiko Epson CorporationInventors: Juri Kato, Kei Kanemoto
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Publication number: 20090237454Abstract: In a method for manufacturing an inkjet recording head which includes a pressure generation chamber supplied with ink fluid and a nozzle opening leading to the pressure generation chamber, the method includes: (a) forming a first trench which serves as the pressure generation chamber on a first surface of a first substrate; (b) forming a second trench which serves as the nozzle opening on a bottom surface of the first trench; (c) forming a sacrificial film on the first trench and the second trench; (d) forming a diaphragm on the sacrificial film as well as on the first surface of the first substrate; (e) forming a piezoelectric element on the diaphragm; (f) grinding a second surface of the first substrate so as to open a bottom surface of the second trench; (g) forming an opening which exposes the sacrificial film on the first surface of the first substrate; and (h) removing the sacrificial film through the opening.Type: ApplicationFiled: March 6, 2009Publication date: September 24, 2009Applicant: SEIKO EPSON CORPORATIONInventor: Kei KANEMOTO
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METHOD FOR MANUFACTURING INK JET RECORDING HEAD, INK JET RECORDING HEAD AND INK JET RECORDING DEVICE
Publication number: 20090237468Abstract: A method for manufacturing an ink jet recording head including a reservoir to which ink is supplied from outside, a pressure generating chamber leading to the reservoir, and a nozzle orifice leading to the pressure generating chamber, includes: a) forming a flow channel forming film on a first face side of a substrate having an integrated circuit; b) forming a groove in the flow channel forming film; c) filling the groove with a sacrificial film; d) forming a vibrating film on the sacrificial film and the flow channel forming film; e) forming a piezoelectric element on the vibrating film; f) forming the reservoir by etching the substrate from a second face side of the substrate to an extent where the sacrificial film is exposed; g) removing the sacrificial film through the reservoir; and h) forming the nozzle orifice in the flow channel forming film.Type: ApplicationFiled: March 19, 2009Publication date: September 24, 2009Applicant: SEIKO EPSON CORPORATIONInventor: Kei Kanemoto -
Patent number: 7569438Abstract: A method of manufacturing a semiconductor device that includes the steps of forming an oxide film on a surface layer section, forming a window section by selectively removing the oxide film, forming a first semiconductor layer, forming a second semiconductor layer, forming a pair of support member holes for exposing the substrate semiconductor layer, forming a support member on the active surface side of the semiconductor substrate, forming an end-exposed surface exposing at least a part of an end of the first semiconductor layer, forming a substrate semiconductor layer exposed surface, removing the first semiconductor layer below the support member by wet etching, filling a hollow section obtained by the wet etching with an oxide film using thermal oxidation, exposing the second semiconductor layer and providing a semiconductor device to the second semiconductor layer.Type: GrantFiled: November 30, 2007Date of Patent: August 4, 2009Assignee: Seiko Epson CorporationInventor: Kei Kanemoto
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Patent number: 7524705Abstract: A method for manufacturing a semiconductor substrate includes forming a first semiconductor layer on a predetermined region of a semiconductor base, forming a second semiconductor layer whose etching selective ratio is smaller than that of the first semiconductor layer on the first semiconductor layer, forming a support member to support the second semiconductor layer on the semiconductor base so as to cover the second semiconductor layer, forming an opening face in the support member to expose a portion of an edge of the first semiconductor layer, etching the first semiconductor layer through the opening face so as to form a cavity between the second semiconductor layer and the semiconductor base, cleaning between the second semiconductor layer and the semiconductor base through the opening face in a condition to remove a residue of the first semiconductor layer, and forming an insulating film in the cavity after cleaned.Type: GrantFiled: July 26, 2006Date of Patent: April 28, 2009Assignee: Seiko Epson CorporationInventor: Kei Kanemoto
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Patent number: 7507643Abstract: A method for manufacturing a semiconductor substrate includes forming a first semiconductor layer on a semiconductor base; forming a second semiconductor layer having a lower etching selection ratio than the first semiconductor layer on the first semiconductor layer; removing a part of the second semiconductor layer and a part of the first semiconductor layer around an element region so as to form a recess for a support, the recess exposing the semiconductor base; forming a support forming layer on the semiconductor base so as to fill the recess and cover the second semiconductor layer; etching a part excluding the recess and the element region so as to form a support and an exposed face exposing a part of an end face of the first semiconductor layer and a part of an end face of the second semiconductor layer located under the support; etching the first semiconductor layer through the exposed face so as to form a cavity between the second semiconductor layer and the semiconductor base; forming a buried insulaType: GrantFiled: November 29, 2006Date of Patent: March 24, 2009Assignee: Seiko Epson CorporationInventor: Kei Kanemoto
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Patent number: 7495287Abstract: A semiconductor device includes a semiconductor layer formed by epitaxial growth in a first region which is obtained by etching a semiconductor substrate to a predetermined depth, a surface of the semiconductor layer having a same height from the bottom of the semiconductor substrate as a height of a surface of the semiconductor substrate, a buried insulating layer buried between the semiconductor substrate and the semiconductor layer and an element isolation region separating each element region in the semiconductor layer and isolating the semiconductor layer from the semiconductor substrate in plan.Type: GrantFiled: January 3, 2007Date of Patent: February 24, 2009Assignee: Seiko Epson CorporationInventors: Hideaki Oka, Kei Kanemoto
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Patent number: 7488666Abstract: A method for manufacturing a semiconductor substrate comprises: forming a silicon on insulator (SOI) area and an element isolation film on a semiconductor base; forming a first semiconductor layer on the semiconductor base in the SOI structure area; forming a second semiconductor layer having an etching selection ratio smaller than an etching selection ratio of the first semiconductor layer on the first semiconductor layer; removing a part of the second semiconductor layer and a part of the first semiconductor layer in the SOI structure area so as to form a recess exposing the semiconductor base and supporting a support; forming a support forming layer on the semiconductor base so as to bury the recess and cover the second semiconductor layer; etching an area excluding the recess, the element area, and an area covering the element isolation film so as to form the support and an opening face exposing a part of end parts of the first semiconductor layer and the second semiconductor layer, the opening face beingType: GrantFiled: November 29, 2006Date of Patent: February 10, 2009Assignee: Seiko Epson CorporationInventor: Kei Kanemoto
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Patent number: 7465641Abstract: Manufacturing a semiconductor device by removing the insulation film in an alignment mark-forming region, depositing a first semiconductor layer, removing the insulation film on the semiconductor substrate after the second semiconductor layer is formed, forming a first exposing region for exposing the semiconductor substrate through the second semiconductor layer and the first semiconductor layer with reference to the second semiconductor layer in the alignment mark-forming region as a first alignment mark for positioning, while forming, on the semiconductor substrate, a second alignment mark, forming a second exposing region for exposing the first semiconductor layer by using the second alignment mark as a reference for positioning, forming a cavity and forming a buried insulation layer in the cavity, and forming a first grate electrode by using the second alignment mark as a reference for positioning.Type: GrantFiled: March 29, 2006Date of Patent: December 16, 2008Assignee: Seiko Epson CorporationInventors: Toshiki Hara, Kei Kanemoto
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Patent number: 7452781Abstract: A method for manufacturing a semiconductor substrate having a silicon-on-insulator (SOI) structure region isolated by a local oxidation of silicon (LOCOS) film and an SOI structure in the region includes forming the LOCOS film so as to make a height from an uppermost surface of a semiconductor member to a top surface of the LOCOS film be higher than a height from the uppermost surface of the semiconductor member to a top surface of the SOI structure, forming a silicon germanium layer and a silicon layer on the SOI structure region on the semiconductor member by epitaxial growth and forming a polysilicon film on a surface of the LOCOS film, forming a recess for a support to support the silicon layer to be a part of the SOI structure, forming the support on the semiconductor member, exposing a side of the silicon germanium layer and the silicon layer underneath the support, forming a cavity by removing the silicon germanium layer having the side exposed, forming the SOI structure by embedding an insulating layeType: GrantFiled: December 14, 2006Date of Patent: November 18, 2008Assignee: Seiko Epson CorporationInventor: Kei Kanemoto
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Publication number: 20080237778Abstract: A method for manufacturing a semiconductor device having a silicon-on-insulator region and a bulk region in a same semiconductor substrate, the method includes: (a) etching the semiconductor substrate in the silicon-on-insulator region so as to form a concave; (b) forming a first semiconductor layer and subsequently a second semiconductor layer on the semiconductor substrate in the silicon-on-insulator region, so as to bury the concave; (c) etching the second semiconductor layer and the first semiconductor layer partially, so as to form a trench which exposes a side surface of the first semiconductor substrate in the silicon-on-insulator region; (d) etching the first semiconductor layer through the trench with an etching condition in which the first semiconductor layer is easier to be etched than the second semiconductor layer, so as to form a cavity between the semiconductor substrate and the second semiconductor layer in the silicon-on-insulator region; and (e) forming a buried insulating film inside the caType: ApplicationFiled: March 24, 2008Publication date: October 2, 2008Applicant: SEIKO EPSON CORPORATIONInventor: Kei KANEMOTO
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Patent number: 7425495Abstract: A method of manufacturing a semiconductor substrate and semiconductor device is disclosed and comprises forming a first monocrystalline semiconductor layer on a semiconductor base material, forming a second monocrystalline semiconductor layer covering the first monocrystalline semiconductor layer, and forming a support hole exposing the semiconductor base. A support layer is formed on the active surface of the semiconductor base material to fill the support hole and covers the second polycrystalline semiconductor layer. A cavity is formed between the second monocrystalline semiconductor layer and the semiconductor base material by selectively etching the first monocrystalline semiconductor layer through the opening surface. A buried insulating layer is formed in the cavity. A planarizing layer is formed on the semiconductor base material and planarized using the second polycrystalline semiconductor layer as an etch stop layer.Type: GrantFiled: December 14, 2006Date of Patent: September 16, 2008Assignee: Seiko Epson CorporationInventor: Kei Kanemoto
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Publication number: 20080206953Abstract: A method for manufacturing a semiconductor device having a silicon-on-insulator region and a bulk region in a same semiconductor substrate, the method including: (a) forming a protection film on the semiconductor substrate in the bulk region; (b) exposing a surface of the semiconductor substrate in the silicon-on-insulator region from under the protection film; (c) forming a first semiconductor layer and subsequently a second semiconductor layer on the semiconductor substrate in the silicon-on-insulator region and in the bulk region, using an epitaxy method after the step (a); (d) etching the first semiconductor layer and the second semiconductor layer partially, so as to form a first trench which exposes a side surface of the first semiconductor layer in the silicon-on-insulator region; (e) etching the first semiconductor layer through the first trench with an etching condition in which the first semiconductor layer is easier to be etched than the second semiconductor layer, so as to form a cavity between thType: ApplicationFiled: February 19, 2008Publication date: August 28, 2008Applicant: SEIKO EPSON CORPORATIONInventor: Kei KANEMOTO
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Publication number: 20080194082Abstract: A method for manufacturing a semiconductor device, includes: (a) forming a SiGe layer on a Si substrate; (b) forming a Si layer on the SiGe layer; (c) forming a dummy pattern made of SiGe in a dummy region of the Si substrate; and (d) wet-etching and removing the SiGe layer formed under the Si layer. In the step (d), an etchant is kept to contact the dummy pattern from before a complete remove of the SiGe layer to an end of the etching.Type: ApplicationFiled: February 4, 2008Publication date: August 14, 2008Applicant: SEIKO EPSON CORPORATIONInventors: Juri KATO, Kei KANEMOTO