Patents by Inventor Kei-Wei Chen

Kei-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240420978
    Abstract: Provided is a chemical-mechanical polishing apparatus, a retaining ring for a chemical-mechanical polishing apparatus, and a chemical-mechanical polishing method. A chemical-mechanical polishing apparatus includes a polishing pad; a polishing head configured to receive a wafer and to hold the wafer against the polishing pad; and a retaining ring configured to engage with the polishing head, wherein the retaining ring is formed with channels configured for flowing a slurry in a flow direction from outside the retaining ring to inside the retaining ring, wherein the channels have a cross-sectional flow area that decreases in the flow direction.
    Type: Application
    Filed: June 14, 2023
    Publication date: December 19, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Chi LIN, Chi-hsiang SHEN, Te-Chien HOU, Tang-Kuei CHANG, Chi-Jen LIU, Hui-Chi HUANG, Kei-Wei CHEN
  • Publication number: 20240412977
    Abstract: A chemical mechanical planarization system includes a chemical mechanical planarization pad that rotates during a chemical mechanical planarization process. A chemical mechanical planarization head places a semiconductor wafer in contact with the chemical mechanical planarization pad during the process. A slurry supply system supplies a slurry onto the pad during the process. A pad conditioner conditions the pad during the process. An impurity removal system removes debris and impurities from the slurry.
    Type: Application
    Filed: July 25, 2024
    Publication date: December 12, 2024
    Inventors: Te-Chien HOU, Po-Chin NIEN, Chih Hung CHEN, Ying-Tsung CHEN, Kei-Wei CHEN
  • Patent number: 12159925
    Abstract: In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: December 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ji-Yin Tsai, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Yee-Chia Yeo
  • Patent number: 12158332
    Abstract: A method of evaluating a thickness of a film on a substrate includes detecting atomic force responses of the film to exposure of electromagnetic radiation in the infrared portion of the electromagnetic spectrum. The use of atomic force microscopy to evaluate thicknesses of thin films avoids underlayer noise commonly encountered when optical metrology techniques are utilized to evaluate film thicknesses. Such underlayer noise adversely impacts the accuracy of the thickness evaluation.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: December 3, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih Hung Chen, Kei-Wei Chen, Te-Ming Kung
  • Publication number: 20240395562
    Abstract: Methods of manufacturing a chemical-mechanical polishing (CMP) slurry and methods of performing CMP process on a substrate comprising metal features are described herein. The CMP slurry may be manufactured using a balanced concentration ratio of chelator additives to inhibitor additives, the ratio being determined based on an electro potential (Ev) value of a metal material of the substrate. The CMP process may be performed on the substrate based on the balanced concentration ratio of chelator additives to inhibitor additives of the CMP slurry.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Chun-Hao Kung, Tung-Kai Chen, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
  • Publication number: 20240395537
    Abstract: Provided are a tool and a method for processing a semiconductor wafer. A processing method includes supporting a semiconductor wafer continuously along a periphery of the semiconductor wafer with an electrically grounded conductive member; and spinning the semiconductor wafer, wherein surface charges induced during spinning are dissipated by movement of electrons from the semiconductor wafer to the electrically grounded conductive member at the periphery of the semiconductor wafer.
    Type: Application
    Filed: May 26, 2023
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-hsiang Shen, Jeng-Chi Lin, Te-Chien Hou, Che-Hao Tu, Tang-Kuei Chang, Kei-Wei Chen, Hui-Chi Huang
  • Publication number: 20240387162
    Abstract: A method of cleaning and polishing a backside surface of a semiconductor wafer is provided. The method includes placing an abrasive brush, comprising an abrasive tape wound around an outer surface of a brush member of the abrasive brush, on the backside surface of the semiconductor wafer. The method also includes rotating the brush member to polish the backside surface of the semiconductor wafer by abrasive grains formed on the abrasive tape and to clean the backside surface of the semiconductor wafer by the brush member which is not covered by the abrasive tape.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: KEI-WEI CHEN, CHIH HUNG CHEN
  • Publication number: 20240383093
    Abstract: Embodiments of the present disclosure relate a CMP tool and methods for planarization a substrate. Particularly, embodiments of the present disclosure provide a substrate transporter for use in a CMP tool. The transporter may be used transport and/or carry substrates among various polishers and cleaners in a CMP tool while preventing the substrates from drying out during transportation. By keeping surfaces of the substrates wet during substrate waiting time or idle time in the CMP tool, embodiments of the present disclosure prevent many types of defects, such as byproducts, agglomerated abrasives, pad debris, slurry residues, from accumulate on the substrate surface during CMP processing, thus improve yields and device performance.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 21, 2024
    Inventors: Te-Chien HOU, Chih Hung CHEN, Kang HUANG, Wen-Pin LIAO, Shich-Chang SUEN, Kei-Wei CHEN
  • Publication number: 20240378362
    Abstract: A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: I-Shuo Liu, Chih-Chun Hsia, Hsin-Ting Chou, Kuanhua Su, William Weilun Hong, Chih Hung Chen, Kei-Wei Chen
  • Publication number: 20240379421
    Abstract: A semiconductor structure includes: a first conductive layer arranged over a substrate; a dielectric layer arranged over the first conductive layer; a second conductive layer arranged within the dielectric layer and electrically connected to the first conductive layer, the second conductive layer including a sidewall distant from the dielectric layer by a width; and a first blocking layer over a surface of the first conductive layer between the second conducive layer and the dielectric layer. The first blocking layer includes at least one element of a precipitant.
    Type: Application
    Filed: July 21, 2024
    Publication date: November 14, 2024
    Inventors: CHUN-WEI HSU, CHIH-CHIEH CHANG, YI-SHENG LIN, JIAN-CI LIN, JENG-CHI LIN, TING-HSUN CHANG, LIANG-GUANG CHEN, JI CUI, KEI-WEI CHEN, CHI-JEN LIU
  • Publication number: 20240367202
    Abstract: A process tool including a polishing pad on a top surface of a wafer platen. A wafer carrier is configured to hold a wafer over the polishing pad. A slurry dispenser is configured to dispense an abrasive slurry including a plurality of charged abrasive particles having a first polarity onto the polishing pad. A first conductive rod is within the wafer platen and coupled to a first voltage supply. A wafer roller is configured to support the wafer. A first wafer brush is arranged beside the wafer roller. A second conductive rod is within the first wafer brush and coupled to a second voltage supply. The first voltage supply is configured to apply a first charge having a second polarity, opposite the first polarity, to the first conductive rod. The second voltage supply is configured to apply a second charge having the second polarity to the second conductive rod.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Chih-Wen Liu, Yeo-Sin Lin, Shu-Wei Hsu, Che-Hao Tu, Hui-Chi Huang, Kei-Wei Chen
  • Publication number: 20240371648
    Abstract: Provided herein are polishing pads in which microcapsules that include a polymer material and are dispersed, as well as methods of making and using the same. Such microcapsules are configured to break open (e.g., when the polishing pad is damaged during the dressing process), which releases the polymer material. When contacted with ultraviolet light the polymer material at least partially cures, healing the damage to the polishing pad. Such polishing pads have a longer lifetime and a more stable remove rate when compared to standard polishing pads.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Inventors: Chun-Hao KUNG, Hui-Chi HUANG, Kei-Wei CHEN, Yen-Ting Chen
  • Publication number: 20240371983
    Abstract: In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Ji-Yin Tsai, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Yee-Chia Yeo
  • Publication number: 20240363404
    Abstract: The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng CHEN, Tang-Kuei CHANG, Yee-Chia YEO, Huicheng CHANG, Wei-Wei LIANG, Ji CUI, Fu-Ming HUANG, Kei-Wei CHEN, Liang-Yin CHEN
  • Publication number: 20240363361
    Abstract: A semiconductor processing tool includes a cleaning chamber configured to perform a post-chemical mechanical polishing/planarization (post-CMP) cleaning operation in an oxygen-free (or in a near oxygen-free) manner. An inert gas may be provided into the cleaning chamber to remove oxygen from the cleaning chamber such that the post-CMP cleaning operation may be performed in an oxygen-free (or in a near oxygen-free) environment. In this way, the post-CMP cleaning operation may be performed in an environment that may reduce oxygen-causing corrosion of metallization layers and/or metallization structures on and/or in the semiconductor wafer, which may increase semiconductor processing yield, may decrease semiconductor processing defects, and/or may increase semiconductor processing quality, among other examples.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Ji CUI, Chih Hung CHEN, Liang-Guang CHEN, Kei-Wei CHEN
  • Patent number: 12128455
    Abstract: A method comprising: providing a slurry to a polishing pad that is disposed on a wafer platen, the slurry comprising a plurality of electrically charged abrasive particles having a first electrical polarity; moving a first side of a wafer into contact with the slurry and the polishing pad; applying a first electrical charge having a second electrical polarity, opposite the first electrical polarity, to a first conductive rod; moving the first side of the wafer away from the polishing pad while the first electrical charge is applied to the first conductive rod; moving a first wafer brush into contact with the first side of the wafer; applying a second electrical charge having the second electrical polarity, opposite the first electrical polarity, to a second conductive rod arranged within the first wafer brush; and moving the first wafer brush away from the first side of the wafer.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: October 29, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wen Liu, Yeo-Sin Lin, Shu-Wei Hsu, Che-Hao Tu, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 12131896
    Abstract: A method of cleaning and polishing a backside surface of a semiconductor wafer is provided. The method includes placing an abrasive brush, comprising an abrasive tape wound around an outer surface of a brush member of the abrasive brush, on the backside surface of the semiconductor wafer. The method also includes rotating the brush member to polish the backside surface of the semiconductor wafer by abrasive grains formed on the abrasive tape and to clean the backside surface of the semiconductor wafer by the brush member which is not covered by the abrasive tape.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kei-Wei Chen, Chih Hung Chen
  • Patent number: 12132107
    Abstract: A semiconductor structure includes a substrate, a first semiconductor fin, a second semiconductor fin, and a first lightly-doped drain (LDD) region. The first semiconductor fin is disposed on the substrate. The first semiconductor fin has a top surface and sidewalls. The second semiconductor fin is disposed on the substrate. The first semiconductor fin and the second semiconductor fin are separated from each other at a nanoscale distance. The first lightly-doped drain (LDD) region is disposed at least in the top surface and the sidewalls of the first semiconductor fin.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung Tsai, Kuo-Feng Yu, Kei-Wei Chen
  • Patent number: 12131944
    Abstract: A slurry composition, a semiconductor structure and a method for forming a semiconductor structure are provided. The slurry composition includes a slurry and a precipitant dispensed in the slurry. The semiconductor structure comprises a blocking layer including at least one element of the precipitant. The method includes using the slurry composition with the precipitant to polish a conductive layer and causing the precipitant to flow into the gap.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Wei Hsu, Chih-Chieh Chang, Yi-Sheng Lin, Jian-Ci Lin, Jeng-Chi Lin, Ting-Hsun Chang, Liang-Guang Chen, Ji Cui, Kei-Wei Chen, Chi-Jen Liu
  • Publication number: 20240339521
    Abstract: A fin-type field effect transistor including a substrate, insulators, a gate stack, a first spacer, a second spacer, and a third spacer is described. The substrate has fins thereon. The insulators are located over the substrate and between the fins. The gate stack is located over the fins and over the insulators. The first spacer is located over the sidewall of the gate stack. The second spacer is located over the first spacer. The first spacer and the second spacer includes carbon. The third spacer is located between the first spacer and the second spacer.
    Type: Application
    Filed: June 18, 2024
    Publication date: October 10, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Kei-Wei CHEN