Patents by Inventor Kei-Wei Chen

Kei-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11664213
    Abstract: A tool and methods of removing films from bevel regions of wafers are disclosed. The bevel film removal tool includes an inner motor nested within an outer motor and a bevel brush secured to the outer motor. The bevel brush is adjustable radially outward to allow the wafer to be inserted in the bevel brush and to be secured to the inner motor. The bevel brush is adjustable radially inward to engage one or more sections of the bevel brush and to bring the bevel brush in contact with a bevel region of the wafer. Once engaged, a solution may be dispensed at the engaged sections of the bevel brush and the inner motor and the outer motor may be rotated such that the bevel brush is rotated against the wafer such that the bevel films of the wafer are both chemically and mechanically removed.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Chi Huang, Jeng-Chi Lin, Pin-Chuan Su, Chien-Ming Wang, Kei-Wei Chen
  • Patent number: 11658065
    Abstract: A method for CMP includes following operations. A metal layer is received. A CMP slurry composition is provided in a CMP apparatus. The CMP slurry composition includes at least a first oxidizer and a second oxidizer different from each other. The first oxidizer is oxidized to form a peroxidant by the second oxidizer. A portion of the metal layer is oxidized to form a first metal oxide by the peroxidant. The first metal oxide is re-oxidized to form a second metal oxide by the second oxidizer.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: May 23, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ji Cui, Fu-Ming Huang, Ting-Kui Chang, Tang-Kuei Chang, Chun-Chieh Lin, Wei-Wei Liang, Chi-Hsiang Shen, Ting-Hsun Chang, Li-Chieh Wu, Hung Yen, Chi-Jen Liu, Liang-Guang Chen, Kei-Wei Chen
  • Publication number: 20230154985
    Abstract: A method of forming a semiconductor structure includes following operations. A substrate including a silicon (Si) layer is received. An amorphous germanium (Ge) layer is formed on the Si layer. A barrier layer is formed over the amorphous Ge layer. The substrate is annealed to transform the Si layer and the Ge layer to form a single crystalline SiGe layer. A Ge concentration is in a positive correlation with a ratio of a thickness of the Ge layer and a thickness of the Si layer.
    Type: Application
    Filed: January 13, 2022
    Publication date: May 18, 2023
    Inventors: TE-MING KUNG, YING-LANG WANG, KEI-WEI CHEN, WEN-HSI LEE, SHU WEI CHANG
  • Publication number: 20230155341
    Abstract: Some implementations described herein provide a laser device. The laser device includes a first portion of the laser device, at a proximal end of the laser device, that includes one or more optical devices, where the first portion is configured to emit first electromagnetic waves having a first wavelength. The laser device includes a second portion of the laser device, at a distal end of the laser device, that includes an optical crystal configured to receive the first electromagnetic waves and to emit second electromagnetic waves having a second wavelength based on reception of the first electromagnetic waves, where the optical crystal includes a thin film coating disposed on an end of the optical crystal, the thin film coating configured to: support emission of the second electromagnetic waves from the optical crystal, and support internal reflection of the first electromagnetic waves within the optical crystal.
    Type: Application
    Filed: February 16, 2022
    Publication date: May 18, 2023
    Inventors: Yu-Hua HSIEH, Ying-Yen TSENG, Wen-Yu KU, Kei-Wei CHEN
  • Patent number: 11633829
    Abstract: A chemical mechanical polishing (CMP) system includes a polishing pad configured to polish a substrate. The CMP system further includes a heating system configured to adjust a temperature of the polishing pad. The heating system comprises at least one heating element spaced apart from the polishing pad. The CMP system further includes a sensor configured to measure the temperature of the polishing pad.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: April 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Sheng Lin, Chi-Hsiang Shen, Chi-Jen Liu, Chun-Wei Hsu, Yang-Chun Cheng, Kei-Wei Chen
  • Patent number: 11637021
    Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: April 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Sheng Lin, Chi-Jen Liu, Chi-Hsiang Shen, Te-Ming Kung, Chun-Wei Hsu, Chia-Wei Ho, Yang-Chun Cheng, William Weilun Hong, Liang-Guang Chen, Kei-Wei Chen
  • Publication number: 20230118617
    Abstract: Provided herein are polishing pads in which microcapsules that include a polymer material and are dispersed, as well as methods of making and using the same. Such microcapsules are configured to break open (e.g., when the polishing pad is damaged during the dressing process), which releases the polymer material. When contacted with ultraviolet light the polymer material at least partially cures, healing the damage to the polishing pad. Such polishing pads have a longer lifetime and a more stable remove rate when compared to standard polishing pads.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 20, 2023
    Inventors: Chun-Hao Kung, Hui-Chi Huang, Kei-Wei Chen, Yen-Ting Chen
  • Patent number: 11631618
    Abstract: Various embodiments provide a thickness sensor and method for measuring a thickness of discrete conductive features, such as conductive lines and plugs. In one embodiment, the thickness sensor generates an Eddy current in a plurality of discrete conductive features, and measures the generated Eddy current generated in the discrete conductive features. The thickness sensor has a small sensor spot size, and amplifies peaks and valleys of the measured Eddy current. The thickness sensor determines a thickness of the discrete conductive features based on a difference between a minimum amplitude value and a maximum amplitude value of the measured Eddy current.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: April 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih Hung Chen, Kei-Wei Chen, Ying-Lang Wang
  • Patent number: 11621342
    Abstract: In an embodiment, a method includes: performing a self-limiting process to modify a top surface of a wafer; after the self-limiting process completes, removing the modified top surface from the wafer; and repeating the performing the self-limiting process and the removing the modified top surface from the wafer until a thickness of the wafer is decreased to a predetermined thickness.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: April 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Hung Chen, Kei-Wei Chen, Ying-Lang Wang
  • Publication number: 20230082084
    Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 16, 2023
    Inventors: JI CUI, FU-MING HUANG, TING-KUI CHANG, TANG-KUEI CHANG, CHUN-CHIEH LIN, WEI-WEI LIANG, LIANG-GUANG CHEN, KEI-WEI CHEN, HUNG YEN, TING-HSUN CHANG, CHI-HSIANG SHEN, LI-CHIEH WU, CHI-JEN LIU
  • Publication number: 20230078573
    Abstract: A planarization method includes: providing a substrate, wherein the substrate includes a first region and a second region having different degrees of hydrophobicity or hydrophilicity, the second region covering an upper surface of the first region; polishing the substrate with a polishing slurry until the upper surface of the first region is exposed; and continuing polishing and performing a surface treatment by the polishing slurry to adjust the degree of hydrophobicity or hydrophilicity of at least one of the first region and the second region. The polishing slurry and the upper surface of the second region have a first contact angle, and the polishing slurry and the upper surface of the first region have a second contact angle. The surface treatment keeps a contact angle difference between the first contact angle and the second contact angle being equal to or less than 30 degrees during the polishing.
    Type: Application
    Filed: June 23, 2022
    Publication date: March 16, 2023
    Inventors: TUNG-KAI CHEN, CHING-HSIANG TSAI, KAO-FENG LIAO, CHIH-CHIEH CHANG, CHUN-HAO KUNG, FANG-I CHIH, HSIN-YING HO, CHIA-JUNG HSU, HUI-CHI HUANG, KEI-WEI CHEN
  • Publication number: 20230064918
    Abstract: A slurry composition, a semiconductor structure and a method for forming a semiconductor structure are provided. The slurry composition includes a slurry and a precipitant dispensed in the slurry. The semiconductor structure comprises a blocking layer including at least one element of the precipitant. The method includes using the slurry composition with the precipitant to polish a conductive layer and causing the precipitant to flow into the gap.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: CHUN-WEI HSU, CHIH-CHIEH CHANG, YI-SHENG LIN, JIAN-CI LIN, JENG-CHI LIN, TING-HSUN CHANG, LIANG-GUANG CHEN, JI CUI, KEI-WEI CHEN, CHI-JEN LIU
  • Publication number: 20230064958
    Abstract: A method of cleaning and polishing a backside surface of a semiconductor wafer is provided. The method includes placing an abrasive brush, comprising an abrasive tape wound around an outer surface of a brush member of the abrasive brush, on the backside surface of the semiconductor wafer. The method also includes rotating the brush member to polish the backside surface of the semiconductor wafer by abrasive grains formed on the abrasive tape and to clean the backside surface of the semiconductor wafer by the brush member which is not covered by the abrasive tape.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: KEI-WEI CHEN, CHIH HUNG CHEN
  • Patent number: 11590627
    Abstract: A method of performing a chemical mechanical planarization (CMP) process includes holding a wafer by a retainer ring attached to a carrier, pressing the wafer against a first surface of a polishing pad, the polishing pad rotating at a first speed, dispensing a slurry on the first surface of the polishing pad, and generating vibrations at the polishing pad.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hao Kung, Shang-Yu Wang, Ching-Hsiang Tsai, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 11594680
    Abstract: A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chang-Miao Liu, Bwo-Ning Chen, Kei-Wei Chen
  • Patent number: 11569387
    Abstract: A semiconductor Fin FET device includes a fin structure disposed over a substrate. The fin structure includes a channel layer. The Fin FET device also includes a gate structure including a gate electrode layer and a gate dielectric layer, covering a portion of the fin structure. Side-wall insulating layers are disposed over both main sides of the gate electrode layer. The Fin FET device includes a source and a drain, each including a stressor layer disposed in a recess formed by removing the fin structure not covered by the gate structure. The stressor layer includes a first to a third stressor layer formed in this order. In the source, an interface between the first stressor layer and the channel layer is located under one of the side-wall insulating layers closer to the source or the gate electrode.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Hsiung Tsai, Kei-Wei Chen
  • Publication number: 20230021149
    Abstract: Some implementations described herein relate to dispensing a slurry onto a polishing pad for a chemical-mechanical planarization (CMP) process. These implementations also involve rotating the polishing pad while the slurry is dispensed onto the polishing pad. Rotation of the polishing pad results in a traversal of the slurry radially outward toward a polishing pad outer edge of the polishing pad. The polishing pad includes a plurality of groove segments and a geometric patterns formed by the plurality of the groove segments impede the flow of the slurry to the polishing pad outer edge.
    Type: Application
    Filed: November 2, 2021
    Publication date: January 19, 2023
    Inventors: Te-Chien HOU, Chih Hung CHEN, Shich-Chang SUEN, Liang-Guang CHEN, Wen-Pin LIAO, Kei-Wei CHEN
  • Patent number: 11551936
    Abstract: Provided herein are polishing pads in which microcapsules that include a polymer material and are dispersed, as well as methods of making and using the same. Such microcapsules are configured to break open (e.g., when the polishing pad is damaged during the dressing process), which releases the polymer material. When contacted with ultraviolet light the polymer material at least partially cures, healing the damage to the polishing pad. Such polishing pads have a longer lifetime and a more stable remove rate when compared to standard polishing pads.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: January 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hao Kung, Hui-Chi Huang, Kei-Wei Chen, Yen-Ting Chen
  • Publication number: 20220415665
    Abstract: A chemical mechanical planarization system includes a chemical mechanical planarization pad that rotates during a chemical mechanical planarization process. A chemical mechanical planarization head places a semiconductor wafer in contact with the chemical mechanical planarization pad during the process. A slurry supply system supplies a slurry onto the pad during the process. A pad conditioner conditions the pad during the process. An impurity removal system removes debris and impurities from the slurry.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 29, 2022
    Inventors: Te-Chien HOU, Po-Chin NIEN, Chih Hung CHEN, Ying-Tsung CHEN, Kei-Wei CHEN
  • Patent number: 11532514
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a conductive feature over a semiconductor substrate and forming a dielectric layer over the conductive feature. The method also includes forming an opening in the dielectric layer to expose the conductive feature. The method further includes forming a conductive material to overfill the opening. In addition, the method includes thinning the conductive material using a chemical mechanical polishing process. A slurry used in the chemical mechanical polishing process includes an iron-containing oxidizer that oxidizes a portion of the conductive material.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Chieh Wu, Kuo-Hsiu Wei, Kei-Wei Chen, Tang-Kuei Chang, Chia Hsuan Lee, Jian-Ci Lin