Patents by Inventor Kei-Wei Chen

Kei-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10535768
    Abstract: A semiconductor structure includes a substrate, a first semiconductor fin, a second semiconductor fin, and a first lightly-doped drain (LDD) region. The first semiconductor fin is disposed on the substrate. The first semiconductor fin has a top surface and sidewalls. The second semiconductor fin is disposed on the substrate. The first semiconductor fin and the second semiconductor fin are separated from each other at a nanoscale distance. The first lightly-doped drain (LDD) region is disposed at least in the top surface and the sidewalls of the first semiconductor fin.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung Tsai, Kuo-Feng Yu, Kei-Wei Chen
  • Publication number: 20200006533
    Abstract: In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.
    Type: Application
    Filed: April 5, 2019
    Publication date: January 2, 2020
    Inventors: Ji-Yin Tsai, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Yee-Chia Yeo
  • Patent number: 10522356
    Abstract: A semiconductor structure includes a substrate, a source/drain (S/D) junction, and an S/D contact. The S/D junction is associated with the substrate and includes a trench-defining wall, a semiconductor layer, and a semiconductor material. The trench-defining wall defines a trench. The semiconductor layer is formed over the trench-defining wall, partially fills the trench, substantially covers the trench-defining wall, and includes germanium. The semiconductor material is formed over the semiconductor layer and includes germanium, a percentage composition of which is greater than a percentage composition of the germanium of the semiconductor layer. The S/D contact is formed over the S/D junction.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hsiung Tsai, Huai-Tei Yang, Kuo-Feng Yu, Kei-Wei Chen
  • Publication number: 20190393107
    Abstract: Various embodiments provide a thickness sensor and method for measuring a thickness of discrete conductive features, such as conductive lines and plugs. In one embodiment, the thickness sensor generates an Eddy current in a plurality of discrete conductive features, and measures the generated Eddy current generated in the discrete conductive features. The thickness sensor has a small sensor spot size, and amplifies peaks and valleys of the measured Eddy current. The thickness sensor determines a thickness of the discrete conductive features based on a difference between a minimum amplitude value and a maximum amplitude value of the measured Eddy current.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Inventors: CHIH HUNG CHEN, KEI-WEI CHEN, YING-LANG WANG
  • Publication number: 20190385909
    Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
    Type: Application
    Filed: August 30, 2019
    Publication date: December 19, 2019
    Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
  • Patent number: 10504782
    Abstract: A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shich-Chang Suen, Kei-Wei Chen, Liang-Guang Chen
  • Publication number: 20190371664
    Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
  • Publication number: 20190337115
    Abstract: A method includes polishing a wafer on a polishing pad, performing conditioning on the polishing pad using a disk of a pad conditioner, and conducting a heat-exchange media into the disk. The heat-exchange media conducted into the disk has a temperature different from a temperature of the polishing pad.
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Inventors: Kei-Wei Chen, Chih Hung Chen
  • Publication number: 20190305107
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a dielectric layer, a contact plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The dielectric layer is positioned over the gate structure and the source/drain structure. The contact plug is positioned passing through the dielectric layer. The contact plug includes a first metal compound including one of group III elements, group IV elements, group V elements or a combination thereof.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Inventors: Kuo-Ju CHEN, Su-Hao LIU, Chun-Hao KUNG, Liang-Yin CHEN, Huicheng CHANG, Kei-Wei CHEN, Hui-Chi HUANG, Kao-Feng LIAO, Chih-Hung CHEN, Jie-Huang HUANG, Lun-Kuang TAN, Wei-Ming YOU
  • Publication number: 20190287852
    Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.
    Type: Application
    Filed: March 15, 2018
    Publication date: September 19, 2019
    Inventors: Che-Liang Chung, Che-Hao Tu, KEI-WEI CHEN, Chih-Wen Liu, You-Shiang Lin, Yi-Ching Liang
  • Publication number: 20190224810
    Abstract: A polishing pad includes a pad layer and one or more polishing structures over an upper surface of the pad layer, where each of the one or more polishing structures has a pre-determined shape and is formed at a pre-determined location of the pad layer, where the one or more polishing structures comprise at least one continuous line shaped segment extending along the upper surface of the pad layer, where each of the one or more polishing structures is a homogeneous material.
    Type: Application
    Filed: July 2, 2018
    Publication date: July 25, 2019
    Inventors: Chih Hung Chen, Kei-Wei Chen, Ying-Lang Wang
  • Patent number: 10350724
    Abstract: A method includes polishing a wafer on a polishing pad, performing conditioning on the polishing pad using a disk of a pad conditioner, and conducting a heat-exchange media into the disk. The heat-exchange media conducted into the disk has a temperature different from a temperature of the polishing pad.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kei-Wei Chen, Chih Hung Chen
  • Publication number: 20190157103
    Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
    Type: Application
    Filed: June 8, 2018
    Publication date: May 23, 2019
    Inventors: TUNG-KAI CHEN, CHING-HSIANG TSAI, KAO-FENG LIAO, CHIH-CHIEH CHANG, CHUN-HAO KUNG, FANG-I CHIH, HSIN-YING HO, CHIA-JUNG HSU, HUI-CHI HUANG, KEI-WEI CHEN
  • Patent number: 10276715
    Abstract: A fin field effect transistor (FinFET) is provided. The FinFET includes a substrate, a gate stack, and strained source and drain regions. The substrate has a semiconductor fin. The gate stack is disposed across the semiconductor fin. Moreover, the strained source and drain regions are located within recesses of the semiconductor fin beside the gate stack. Moreover, at least one of the strained source and drain regions has a top portion and a bottom portion, the bottom portion is connected to the top portion, and a bottom width of the top portion is greater than a top width of the bottom portion.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Kuo-Feng Yu, Kei-Wei Chen
  • Publication number: 20190109213
    Abstract: A structure includes a semiconductor substrate, a source epitaxial structure, a drain epitaxial structure, and a gate stack. The source epitaxial structure is in the semiconductor substrate. The source epitaxial structure has a top surface, and the top surface of the source epitaxial structure comprises hydrogen. The drain epitaxial structure is in the semiconductor substrate. The gate stack is over the semiconductor substrate and between the source epitaxial structure and the drain epitaxial structure.
    Type: Application
    Filed: November 27, 2018
    Publication date: April 11, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung TSAI, Kei-Wei CHEN
  • Publication number: 20190099853
    Abstract: An abrasive slurry composition for chemical mechanical planarization/polishing (CMP) is provided. The abrasive slurry includes colloidal alumina, a dispersant, and a pH buffer. The colloidal alumina has a particle size of between about 5 nm and about 100 nm. The colloidal alumina may be alpha phase material having a first hardness of about 9 Mohs, or gamma phase material having a second hardness of about 8 Mohs. The abrasive slurry may further include polyacrylic acid (PAA), a down-force enhancer, or a polish-rate inhibitor.
    Type: Application
    Filed: July 2, 2018
    Publication date: April 4, 2019
    Inventors: Shich-Chang Suen, Kei-Wei Chen, Liang-Guang Chen
  • Publication number: 20190103312
    Abstract: A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.
    Type: Application
    Filed: August 16, 2018
    Publication date: April 4, 2019
    Inventors: Shich-Chang Suen, Kei-Wei Chen, Liang-Guang Chen
  • Publication number: 20190099854
    Abstract: A polishing platform of a polishing apparatus includes a platen, a polishing pad, and an electric field element disposed between the platen and the polishing pad. The polishing apparatus further includes a controller configured to apply voltages to the electric field element. A first voltage is applied to the electric field element to attract charged particles of a polishing slurry toward the polishing pad. The attracted particles reduce overall topographic variation of a polishing surface presented to a workpiece for polishing. A second voltage is applied to the electric field element to attract additional charged particles of the polishing slurry toward the polishing pad. The additional attracted particles further reduce overall topographic variation of the polishing surface presented to the workpiece. A third voltage is applied to the electric field element to repel charged particles of the polishing slurry away from the polishing pad for improved cleaning thereof.
    Type: Application
    Filed: July 10, 2018
    Publication date: April 4, 2019
    Inventors: Shich-Chang Suen, Liang-Guang Chen, Kei-Wei Chen
  • Patent number: 10201887
    Abstract: A polishing pad is provided. The polishing pad includes a base layer, a top layer, and multiple grooves. The top layer is located over the base layer and has a polishing surface and a bottom surface opposite to each other. The bottom surface is connected to the base layer. The grooves are formed on the bottom surface of the top layer.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hung Chen, Kei-Wei Chen
  • Publication number: 20190030675
    Abstract: A method includes polishing a wafer on a polishing pad, performing conditioning on the polishing pad using a disk of a pad conditioner, and conducting a heat-exchange media into the disk. The heat-exchange media conducted into the disk has a temperature different from a temperature of the polishing pad.
    Type: Application
    Filed: July 31, 2017
    Publication date: January 31, 2019
    Inventors: Kei-Wei Chen, Chih Hung Chen