Abstract: An amplifier includes: a first signal source that outputs a first and a second frequency signals; a second signal source that outputs the first and the second frequency signals; a first amplifier that receives and amplifies the signal output from the first signal source; a second amplifier that receives and amplifies the signal output from the second signal source; and an output combiner that combines the signals amplified by the first amplifier and the second amplifier, and operates so that a phase difference between the first frequency signals input to the first and the second amplifier amplifiers and that between the second frequency signals input to the first and the second amplifiers satisfy a relational equation in which intermodulation distortion components of those are in opposite phases.

Abstract: A Doherty amplifier includes: a carrier amplifier that amplifies a first signal; a peak amplifier that amplifies a second signal; and a synthesis circuit that synthesizes the first signal amplified by the carrier amplifier and the second signal amplified by the peak amplifier, and the synthesis circuit includes a bandpass filter circuit that includes parasitic capacitances at respective output sides of the carrier amplifier and the peak amplifier as capacitors.

Abstract: A Doherty amplifier is configured in such a way that a phase adjustment circuit adjusts either the phase of a return signal going to a first auxiliary amplification element as a result of passage of a first signal amplified by a second main amplification element through a second auxiliary amplification element as the return signal, or the phase of the return signal going to the second auxiliary amplification element as a result of reflection of the return signal by the first auxiliary amplification element, at a time of a backoff operation of the second auxiliary amplification element, in such a way that the sum of the phase of the return signal going to the first auxiliary amplification element and the phase of the return signal going to the second auxiliary amplification element is not equal to 0 degrees in the operating frequency band of the first signal.

Abstract: A Doherty amplifier includes: a transistor for a carrier amplifier; a transistor for a peak amplifier; a transmission line connected between an output terminal of the transistor for the carrier amplifier and an output terminal of the transistor for the peak amplifier; a stub that is connected in parallel to the output terminal of the transistor for the peak amplifier and that is capacitive and inductive in a working frequency band; and an output matching circuit connected to the output terminal of the transistor for the peak amplifier, the transmission line, and an output load, the output matching circuit to transform an impedance of the output load into an impedance lower than the impedance of the output load.

Abstract: Included is a compensation circuit having one end connected to another end of a first output circuit and another end of a second output circuit and another end grounded, the compensation circuit having an electrical length of 90 degrees at a first operation frequency and an electrical length of 45 degrees at a second operation frequency which is half of the first operation frequency.

Abstract: A Doherty amplifier includes a carrier amplifier, a peaking amplifier, and a phase compensation circuit. The carrier amplifier 11 includes a main amplifying element and a parasitic element, and the peaking amplifier includes an auxiliary amplifying element and a parasitic element. The phase compensation circuit has a negative electrical length that allows a total electrical length of a signal transmission path starting from an output source of the main amplifying element to a power combiner to become 180°×N?90° where N is a positive integer. In addition, a signal transmission path starting from an output source of the auxiliary amplifying element to the power combiner has an electrical length of 180°×M?180° where M is a positive integer.

Abstract: A conventional Doherty amplifier requires a load modulation line having an electrical length of 90 degrees, a frequency compensation line having an electrical length of an integral (n) multiple of 180 degrees, and an input phase adjustment line having an electrical length corresponding to a difference (180°×n?90°) between the electrical length of the load modulation line and the electrical length of the frequency compensation line. Thus, the conventional Doherty amplifier has a problem of an increase in circuit size.

Abstract: Parallel inductors include a first metal wire (8a or 8b) for connecting a drain terminal (2) and a first metal pattern (7a or 7b), and a second metal wire (10a or 10b) for connecting the first metal pattern (7a or 7b) and a second metal pattern (9a or 9b). The second metal wires (10a and 10b) are each positioned between the corresponding first metal wire (8a or 8b) and a corresponding third metal wire (12a or 12b) for connecting the drain terminal (2) and a third metal pattern (11). The direction of current through the second metal wires (10a and 10b) is opposite to the direction of current through each of the first metal wire (8a or 8b) and the third metal wire (12a or 12b).

Abstract: Included is a compensation circuit (9) having one end connected to another end of a first output circuit (7) and another end of a second output circuit (8) and another end grounded, the compensation circuit having an electrical length of 90 degrees at a first operation frequency and an electrical length of 45 degrees at a second operation frequency which is half of the first operation frequency.

Abstract: In a case where the power of a signal to be amplified is greater than or equal to a threshold value, a signal distributor (2) outputs one of signals to a carrier amplifier (6), outputs another signal, a phase of which is 90 degrees behind that of the one of the signals, to a peak amplifier (8), and adjusts a phase shift amount of a signal shifted by a phase shifter (7) depending on the frequency of the signal to be amplified. In a case where the power of the signal to be amplified is less than the threshold value, the signal distributor (2) outputs the one of the signals to the carrier amplifier (6) without outputting the other signal to the peak amplifier (8).

Abstract: In a Doherty amplifier including a carrier amplifier (6) and a peaking amplifier (8) connected in parallel with each other, a compensation circuit (9) for causing an impedance seen from an output end (9a) of the compensation circuit (9) toward the peaking amplifier (8) to be open within a used frequency range and compensating for frequency dependence of an impedance seen from an output of a combiner (10) toward the combiner (10) in a state in which the peaking amplifier (8) is not operating is arranged between the peaking amplifier (8) and the combiner (10). This achieves a wider bandwidth without making the circuit larger in size and more complicated.

Abstract: A Doherty amplifier includes a carrier amplifier, a peaking amplifier, and a phase compensation circuit. The carrier amplifier 11 includes a main amplifying element and a parasitic element, and the peaking amplifier includes an auxiliary amplifying element and a parasitic element. The phase compensation circuit has a negative electrical length that allows a total electrical length of a signal transmission path starting from an output source of the main amplifying element to a power combiner to become 180°×N?90° where N is a positive integer. In addition, a signal transmission path starting from an output source of the auxiliary amplifying element to the power combiner has an electrical length of 180°×M?180° where M is a positive integer.

Abstract: Provided is a load modulation amplifier including: a high frequency circuit board; and on the board, an input distribution circuit unit (DC) including: a distributor for dividing one input signal into two signals IS1 and IS2; and a phase delay circuit formed on a signal line for the divided IS2; a carrier amplifier (CA) including a first high frequency transistor for amplifying the IS1; a peak amplifier (PA) including a second high frequency transistor and for amplifying the IS2; and an output combination circuit (OCCU) including: a 90-degree phase delay circuit (90DC) formed on a signal line for output of the CA; a combiner for combining output of the 90DC and output of the PA; and an impedance conversion circuit for converting an output impedance of the combiner. The CA and the PA are directly connected to the OCCU without converting an output impedance.

Abstract: A Wilkinson power divider includes: ?-type LPFs connected to an input terminal; a T-type HPF having one end connected to one of the ?-type LPFs and having another end connected to a carrier amplifier; another T-type HPF having one end connected to another one of the ?-type LPFs and having another end connected to a ?/4 line; and an isolation resistor connected to connection points.

Abstract: In a Doherty amplifier including a carrier amplifier (6) and a peaking amplifier (8) connected in parallel with each other, a compensation circuit (9) for causing an impedance seen from an output end (9a) of the compensation circuit (9) toward the peaking amplifier (8) to be open within a used frequency range and compensating for frequency dependence of an impedance seen from an output of a combiner (10) toward the combiner (10) in a state in which the peaking amplifier (8) is not operating is arranged between the peaking amplifier (8) and the combiner (10). This achieves a wider bandwidth without making the circuit larger in size and more complicated.

Abstract: Parallel inductors include a first metal wire (8a or 8b) for connecting a drain terminal (2) and a first metal pattern (7a or 7b), and a second metal wire (10a or 10b) for connecting the first metal pattern (7a or 7b) and a second metal pattern (9a or 9b). The second metal wires (10a and 10b) are each positioned between the corresponding first metal wire (8a or 8b) and a corresponding third metal wire (12a or 12b) for connecting the drain terminal (2) and a third metal pattern (11). The direction of current through the second metal wires (10a and 10b) is opposite to the direction of current through each of the first metal wire (8a or 8b) and the third metal wire (12a or 12b).

Abstract: Provided is a load modulation amplifier including: a high frequency circuit board; and on the board, an input distribution circuit unit (DC) including: a distributor for dividing one input signal into two signals IS1 and IS2; and a phase delay circuit formed on a signal line for the divided IS2; a carrier amplifier (CA) including a first high frequency transistor for amplifying the IS1; a peak amplifier (PA) including a second high frequency transistor and for amplifying the IS2; and an output combination circuit (OCCU) including: a 90-degree phase delay circuit (90DC) formed on a signal line for output of the CA; a combiner for combining output of the 90DC and output of the PA; and an impedance conversion circuit for converting an output impedance of the combiner. The CA and the PA are directly connected to the OCCU without converting an output impedance.

Abstract: A Wilkinson power divider includes: ?-type LPFs connected to an input terminal; a T-type HPF having one end connected to one of the ?-type LPFs and having another end connected to a carrier amplifier; another T-type HPF having one end connected to another one of the ?-type LPFs and having another end connected to a ?/4 line; and an isolation resistor connected to connection points.

Abstract: A semiconductor integrated circuit is provided with: a memory under test; a test-result-storage memory; a test-data generation part for generating in a sequential manner a test address signal and test data for supplying to the memory under test; and a control circuit. The control circuit includes a delay circuit, which, when the control circuit stores in a sequential manner in the test-result-storage memory a test result according to the test address signal and test data in the memory under test, delays the storage-destination address signal in the test-result-storage memory from the test address signal set in the memory under test, in accordance with a time delay that includes at the least the latency from the setting of the test address signal in the memory under test to the reading out of the test data.

Abstract: A memory test circuit includes a counter circuit that outputs a set signal that is set to the first set value or the second set value alternately in a cycle of the clock signal, an OR circuit that calculates a logical sum of the set signal and the input signal each time when the set signal is output from the counter circuit and outputs a control signal indicating the logical sum of the set signal and the input signal, and a test pattern generation circuit that generates the test pattern for causing the memory to operate in each first cycle if a set value of the control signal is the first set value, or generates the test pattern for causing the memory to operate in each second cycle if the set value of the control signal is the second set value.