Patents by Inventor Keigo Nakatani

Keigo Nakatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10911003
    Abstract: A Doherty amplifier includes a carrier amplifier, a peaking amplifier, and a phase compensation circuit. The carrier amplifier 11 includes a main amplifying element and a parasitic element, and the peaking amplifier includes an auxiliary amplifying element and a parasitic element. The phase compensation circuit has a negative electrical length that allows a total electrical length of a signal transmission path starting from an output source of the main amplifying element to a power combiner to become 180°×N?90° where N is a positive integer. In addition, a signal transmission path starting from an output source of the auxiliary amplifying element to the power combiner has an electrical length of 180°×M?180° where M is a positive integer.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: February 2, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Keigo Nakatani, Shintaro Shinjo, Koji Yamanaka
  • Publication number: 20210006208
    Abstract: A conventional Doherty amplifier requires a load modulation line having an electrical length of 90 degrees, a frequency compensation line having an electrical length of an integral (n) multiple of 180 degrees, and an input phase adjustment line having an electrical length corresponding to a difference (180°×n?90°) between the electrical length of the load modulation line and the electrical length of the frequency compensation line. Thus, the conventional Doherty amplifier has a problem of an increase in circuit size.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 7, 2021
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shuichi SAKATA, Shintaro SHINJO, Keigo NAKATANI, Koji YAMANAKA
  • Patent number: 10748860
    Abstract: Parallel inductors include a first metal wire (8a or 8b) for connecting a drain terminal (2) and a first metal pattern (7a or 7b), and a second metal wire (10a or 10b) for connecting the first metal pattern (7a or 7b) and a second metal pattern (9a or 9b). The second metal wires (10a and 10b) are each positioned between the corresponding first metal wire (8a or 8b) and a corresponding third metal wire (12a or 12b) for connecting the drain terminal (2) and a third metal pattern (11). The direction of current through the second metal wires (10a and 10b) is opposite to the direction of current through each of the first metal wire (8a or 8b) and the third metal wire (12a or 12b).
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 18, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Keigo Nakatani, Yuji Komatsuzaki, Shintaro Shinjo, Koji Yamanaka, Shohei Imai
  • Publication number: 20200244227
    Abstract: Included is a compensation circuit (9) having one end connected to another end of a first output circuit (7) and another end of a second output circuit (8) and another end grounded, the compensation circuit having an electrical length of 90 degrees at a first operation frequency and an electrical length of 45 degrees at a second operation frequency which is half of the first operation frequency.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Keigo NAKATANI, Yuji KOMATSUZAKI, Shuichi SAKATA, Shintaro SHINJO, Koji YAMANAKA
  • Publication number: 20200136564
    Abstract: In a case where the power of a signal to be amplified is greater than or equal to a threshold value, a signal distributor (2) outputs one of signals to a carrier amplifier (6), outputs another signal, a phase of which is 90 degrees behind that of the one of the signals, to a peak amplifier (8), and adjusts a phase shift amount of a signal shifted by a phase shifter (7) depending on the frequency of the signal to be amplified. In a case where the power of the signal to be amplified is less than the threshold value, the signal distributor (2) outputs the one of the signals to the carrier amplifier (6) without outputting the other signal to the peak amplifier (8).
    Type: Application
    Filed: July 27, 2017
    Publication date: April 30, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Keigo NAKATANI, Shuichi SAKATA, Shintaro SHINJO, Koji YAMANAKA
  • Patent number: 10608594
    Abstract: In a Doherty amplifier including a carrier amplifier (6) and a peaking amplifier (8) connected in parallel with each other, a compensation circuit (9) for causing an impedance seen from an output end (9a) of the compensation circuit (9) toward the peaking amplifier (8) to be open within a used frequency range and compensating for frequency dependence of an impedance seen from an output of a combiner (10) toward the combiner (10) in a state in which the peaking amplifier (8) is not operating is arranged between the peaking amplifier (8) and the combiner (10). This achieves a wider bandwidth without making the circuit larger in size and more complicated.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: March 31, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuji Komatsuzaki, Shintaro Shinjo, Keigo Nakatani, Shohei Imai
  • Publication number: 20200091871
    Abstract: A Doherty amplifier includes a carrier amplifier, a peaking amplifier, and a phase compensation circuit. The carrier amplifier 11 includes a main amplifying element and a parasitic element, and the peaking amplifier includes an auxiliary amplifying element and a parasitic element. The phase compensation circuit has a negative electrical length that allows a total electrical length of a signal transmission path starting from an output source of the main amplifying element to a power combiner to become 180°×N?90° where N is a positive integer. In addition, a signal transmission path starting from an output source of the auxiliary amplifying element to the power combiner has an electrical length of 180°×M?180° where M is a positive integer.
    Type: Application
    Filed: January 24, 2017
    Publication date: March 19, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Keigo NAKATANI, Shintaro SHINJO, Koji YAMANAKA
  • Patent number: 10523158
    Abstract: Provided is a load modulation amplifier including: a high frequency circuit board; and on the board, an input distribution circuit unit (DC) including: a distributor for dividing one input signal into two signals IS1 and IS2; and a phase delay circuit formed on a signal line for the divided IS2; a carrier amplifier (CA) including a first high frequency transistor for amplifying the IS1; a peak amplifier (PA) including a second high frequency transistor and for amplifying the IS2; and an output combination circuit (OCCU) including: a 90-degree phase delay circuit (90DC) formed on a signal line for output of the CA; a combiner for combining output of the 90DC and output of the PA; and an impedance conversion circuit for converting an output impedance of the combiner. The CA and the PA are directly connected to the OCCU without converting an output impedance.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: December 31, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shintaro Shinjo, Yuji Komatsuzaki, Keigo Nakatani, Koji Yamanaka
  • Patent number: 10340855
    Abstract: A Wilkinson power divider includes: ?-type LPFs connected to an input terminal; a T-type HPF having one end connected to one of the ?-type LPFs and having another end connected to a carrier amplifier; another T-type HPF having one end connected to another one of the ?-type LPFs and having another end connected to a ?/4 line; and an isolation resistor connected to connection points.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: July 2, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuji Komatsuzaki, Shintaro Shinjo, Keigo Nakatani, Takaaki Yoshioka
  • Publication number: 20190149097
    Abstract: In a Doherty amplifier including a carrier amplifier (6) and a peaking amplifier (8) connected in parallel with each other, a compensation circuit (9) for causing an impedance seen from an output end (9a) of the compensation circuit (9) toward the peaking amplifier (8) to be open within a used frequency range and compensating for frequency dependence of an impedance seen from an output of a combiner (10) toward the combiner (10) in a state in which the peaking amplifier (8) is not operating is arranged between the peaking amplifier (8) and the combiner (10). This achieves a wider bandwidth without making the circuit larger in size and more complicated.
    Type: Application
    Filed: May 18, 2016
    Publication date: May 16, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yuji KOMATSUZAKI, Shintaro SHINJO, Keigo NAKATANI, Shohei IMAI
  • Publication number: 20190148315
    Abstract: Parallel inductors include a first metal wire (8a or 8b) for connecting a drain terminal (2) and a first metal pattern (7a or 7b), and a second metal wire (10a or 10b) for connecting the first metal pattern (7a or 7b) and a second metal pattern (9a or 9b). The second metal wires (10a and 10b) are each positioned between the corresponding first metal wire (8a or 8b) and a corresponding third metal wire (12a or 12b) for connecting the drain terminal (2) and a third metal pattern (11). The direction of current through the second metal wires (10a and 10b) is opposite to the direction of current through each of the first metal wire (8a or 8b) and the third metal wire (12a or 12b).
    Type: Application
    Filed: July 1, 2016
    Publication date: May 16, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Keigo NAKATANI, Yuji KOMATSUZAKI, Shintaro SHINJO, Koji YAMANAKA, Shohei IMAI
  • Publication number: 20190028062
    Abstract: Provided is a load modulation amplifier including: a high frequency circuit board; and on the board, an input distribution circuit unit (DC) including: a distributor for dividing one input signal into two signals IS1 and IS2; and a phase delay circuit formed on a signal line for the divided IS2; a carrier amplifier (CA) including a first high frequency transistor for amplifying the IS1; a peak amplifier (PA) including a second high frequency transistor and for amplifying the IS2; and an output combination circuit (OCCU) including: a 90-degree phase delay circuit (90DC) formed on a signal line for output of the CA; a combiner for combining output of the 90DC and output of the PA; and an impedance conversion circuit for converting an output impedance of the combiner. The CA and the PA are directly connected to the OCCU without converting an output impedance.
    Type: Application
    Filed: February 23, 2016
    Publication date: January 24, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shintaro SHINJO, Yuji KOMATSUZAKI, Keigo NAKATANI, Koji YAMANAKA
  • Publication number: 20180287566
    Abstract: A Wilkinson power divider includes: ?-type LPFs connected to an input terminal; a T-type HPF having one end connected to one of the ?-type LPFs and having another end connected to a carrier amplifier; another T-type HPF having one end connected to another one of the ?-type LPFs and having another end connected to a ?/4 line; and an isolation resistor connected to connection points.
    Type: Application
    Filed: January 5, 2016
    Publication date: October 4, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yuji KOMATSUZAKI, Shintaro SHINJO, Keigo NAKATANI, Takaaki YOSHIOKA
  • Publication number: 20140340975
    Abstract: A semiconductor integrated circuit is provided with: a memory under test; a test-result-storage memory; a test-data generation part for generating in a sequential manner a test address signal and test data for supplying to the memory under test; and a control circuit. The control circuit includes a delay circuit, which, when the control circuit stores in a sequential manner in the test-result-storage memory a test result according to the test address signal and test data in the memory under test, delays the storage-destination address signal in the test-result-storage memory from the test address signal set in the memory under test, in accordance with a time delay that includes at the least the latency from the setting of the test address signal in the memory under test to the reading out of the test data.
    Type: Application
    Filed: July 30, 2014
    Publication date: November 20, 2014
    Inventor: Keigo NAKATANI
  • Patent number: 8412983
    Abstract: A memory test circuit includes a counter circuit that outputs a set signal that is set to the first set value or the second set value alternately in a cycle of the clock signal, an OR circuit that calculates a logical sum of the set signal and the input signal each time when the set signal is output from the counter circuit and outputs a control signal indicating the logical sum of the set signal and the input signal, and a test pattern generation circuit that generates the test pattern for causing the memory to operate in each first cycle if a set value of the control signal is the first set value, or generates the test pattern for causing the memory to operate in each second cycle if the set value of the control signal is the second set value.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: April 2, 2013
    Assignee: Fujitsu Limited
    Inventor: Keigo Nakatani
  • Patent number: 8093936
    Abstract: According to an aspect of the embodiment, a skew detecting unit includes at least one over delay path or racing path for detecting skew. A clock adjusting unit sets a set value of delay based on the skew detected by the skew detecting unit. A clock cell adjusts delay in a first clock according to the set value of the delay, and outputs the result as a second clock.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: January 10, 2012
    Assignee: Fujitsu Limited
    Inventor: Keigo Nakatani
  • Patent number: 7999648
    Abstract: A wire-wound coil has a characteristic impedance that can be flexibly adjusted and can be prevented from varying undesirably. In the coil of the present invention, a primary wire part 18A and a secondary wire part 18B are wound around the surface of a core portion 14 so as to be separated from each other by a fixed distance. At the same time, at least one portion the secondary wire part 18B in a prior turn section 19X and at least one portion of the primary wire part 18A in a subsequent turn section 19Y are in close contact with each other, wherein the wire parts 18A and 18B are wound in different turns and are adjacent to each other on the same surface of the core portion 14. A method for manufacturing the wire-wound coil is also disclosed.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: August 16, 2011
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Keigo Nakatani, Yoshie Nishikawa
  • Patent number: 7804372
    Abstract: A ring oscillator includes an odd number of unit circuits connected in series each of which includes an inverter. Each of the unit circuits includes the inverter and a MOSFET. The MOSFET is an FET which is a temperature sensor, and uses a drain-source leakage current in a state that the FET is normally turned off.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: September 28, 2010
    Assignee: Fujitsu Limited
    Inventor: Keigo Nakatani
  • Publication number: 20100148912
    Abstract: A wire-wound coil has a characteristic impedance that can be flexibly adjusted and can be prevented from varying undesirably. In the coil of the present invention, a primary wire part 18A and a secondary wire part 18B are wound around the surface of a core portion 14 so as to be separated from each other by a fixed distance. At the same time, at least one portion the secondary wire part 18B in a prior turn section 19X and at least one portion of the primary wire part 18A in a subsequent turn section 19Y are in close contact with each other, wherein the wire parts 18A and 18B are wound in different turns and are adjacent to each other on the same surface of the core portion 14. A method for manufacturing the wire-wound coil is also disclosed.
    Type: Application
    Filed: February 24, 2010
    Publication date: June 17, 2010
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Keigo NAKATANI, Yoshie NISHIKAWA
  • Publication number: 20100066424
    Abstract: According to an aspect of the embodiment, a skew detecting unit includes at least one over delay path or racing path for detecting skew. A clock adjusting unit sets a set value of delay based on the skew detected by the skew detecting unit. A clock cell adjusts delay in a first clock according to the set value of the delay, and outputs the result as a second clock.
    Type: Application
    Filed: September 15, 2009
    Publication date: March 18, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Keigo NAKATANI