Patents by Inventor Keiichi Fujii

Keiichi Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7649383
    Abstract: A plurality of transistors are connected between an I2C bus operating at a first voltage level and an I2C bus operating at a second voltage level and a main control electrode of at least one transistor is connected to a first power supply terminal and a main control electrode of the other at least one transistor is connected to an intermediate level between the first voltage level and the second voltage level, whereby a withstand voltage required to a transistor of the bidirectional level shift circuit of the I2C bus can be lowered.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: January 19, 2010
    Assignee: Panasonic Corporation
    Inventors: Hitoshi Kobayashi, Keiichi Fujii
  • Patent number: 7605638
    Abstract: A semiconductor integrated circuit that suppresses steep changes of an output voltage when starting of a charge pump circuit to suppress transient displacement of output of a circuit block operating independently of the charge pump circuit is provided. A semiconductor integrated circuit has: a charge pump circuit which charges a first capacitor with an input voltage, transfers a charge accumulated in the first capacitor to a second capacitor, outputs, as an output voltage, a voltage of the second capacitor, and is capable of changing over a capability of charging the second capacitor; a first circuit block that receives a positive voltage and a grounding potential; and a second circuit block that receives the positive voltage and the output voltage of the charge pump. The semiconductor integrated circuit suppresses the charging capability by the charge pump circuit when starting of the charge pump circuit.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: October 20, 2009
    Assignee: Panasonic Corporation
    Inventors: Toshinobu Nagasawa, Taku Kobayashi, Tetsushi Toyooka, Keiichi Fujii
  • Patent number: 7518431
    Abstract: A semiconductor integrated circuit includes a charge pump circuit that repeats charge and discharge of a capacitor based on a clock signal when an ON/OFF control voltage is ON; a first delay circuit that delays the ON/OFF control voltage; a switch that shorts an output of the charge pump circuit and a GND input terminal when the delayed ON/OFF control voltage is OFF and opens when the delayed ON/OFF control voltage is ON; a first circuit block that is driven by a power voltage which is supplied from a power source input terminal and the charge pump circuit; and a second circuit block that is driven by a power voltage which is supplied from the power source input terminal and the GND input terminal. The first and second circuit blocks are mounted on the same semiconductor integrated circuit chip.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: April 14, 2009
    Assignee: Panasonic Corporation
    Inventors: Taku Kobayashi, Keiichi Fujii
  • Patent number: 7474161
    Abstract: While a charge pump activation/deactivation control circuit is outputting a high level signal, MOS transistors for short-circuiting a flying capacitor are off, and the charge pump circuit operates normally. When the charge pump activation/deactivation control circuit outputs a low level signal, the MOS transistors for short-circuiting the flying capacitor are turned on, and the charge pump circuit is deactivated. Consequently, the voltages at the terminals of the flying capacitor are the same and the charge charged therein is discharged. Therefore, when the charge pump circuit is activated again, the initial amount of charge charged to the flying capacitor is zero. Consequently, no large current flows through an output capacitor in the first discharging cycle after the re-activation.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: January 6, 2009
    Assignee: Panasonic Corporation
    Inventors: Satoshi Azuhata, Toshinobu Nagasawa, Tetsushi Toyooka, Keiichi Fujii
  • Publication number: 20080218213
    Abstract: A plurality of transistors are connected between an I2C bus operating at a first voltage level and an I2C bus operating at a second voltage level and a main control electrode of at least one transistor is connected to a first power supply terminal and a main control electrode of the other at least one transistor is connected to an intermediate level between the first voltage level and the second voltage level, whereby a withstand voltage required to a transistor of the bidirectional level shift circuit of the I2C bus can be lowered.
    Type: Application
    Filed: March 5, 2008
    Publication date: September 11, 2008
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hitoshi Kobayashi, Keiichi Fujii
  • Patent number: 7388434
    Abstract: In a BTL amplifier of the present invention, between first and third transistor parts which are laterally adjacent, directions of semiconductor regions are parallel. Between the first and second transistor parts and the third and fourth transistor parts, each which are longitudinally adjacent, directions of semiconductor regions are perpendicular. The first and the third transistor parts are connected to a power supply terminal through a first wire. The second and the fourth transistor parts are connected to a ground terminal through a second wire. The first and the second transistor parts are connected to a first output terminal through a third wire. The third and the fourth transistor parts are connected to a second output terminal through a fourth wire.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: June 17, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Makoto Yamamoto, Keiichi Fujii
  • Publication number: 20080122522
    Abstract: A semiconductor integrated circuit that suppresses steep changes of an output voltage when starting of a charge pump circuit to suppress transient displacement of output of a circuit block operating independently of the charge pump circuit is provided. A semiconductor integrated circuit has: a charge pump circuit which charges a first capacitor with an input voltage, transfers a charge accumulated in the first capacitor to a second capacitor, outputs, as an output voltage, a voltage of the second capacitor, and is capable of changing over a capability of charging the second capacitor; a first circuit block that receives a positive voltage and a grounding potential; and a second circuit block that receives the positive voltage and the output voltage of the charge pump. The semiconductor integrated circuit suppresses the charging capability by the charge pump circuit when starting of the charge pump circuit.
    Type: Application
    Filed: July 3, 2007
    Publication date: May 29, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Toshinobu Nagasawa, Taku Kobayashi, Tetsushi Toyooka, Keiichi Fujii
  • Patent number: 7377691
    Abstract: A radiographic apparatus obtains lag-free radiation detection signals with lag-behind parts removed from radiation detection signals taken from a flat panel X-ray detector as X rays are emitted from an X-ray tube. The lag-behind parts are removed by a recursive computation on an assumption that the lag-behind part included in each X-ray detection signal is due to an impulse response formed of exponential functions, N in number, with different attenuation time constants. X-ray images are created from the lag-free radiation detection signals.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: May 27, 2008
    Assignee: Shimadzu Corporation
    Inventors: Shoichi Okamura, Keiichi Fujii, Susumu Adachi, Shinya Hirasawa, Toshinori Yoshimuta, Koichi Tanabe, Masatomo Kaino, Hiroshi Koyama
  • Patent number: 7359693
    Abstract: A tuner module comprising a tuner and a tuner enclosure. The tuner includes a substrate containing filter coils and the tuner enclosure includes at least one partition plate placed between filter coils of the tuner to improve the isolation between the filter coils. The substrate may also contain plated through holes placed beneath a partition plate which further improves isolation between the filter coils. In some embodiments, the substrate is comprised of a coil layer having a planar coil, a shield layer, and a dielectric layer. The dielectric layer is placed between the coil and shield layers and provides a distance between the two layers to achieve a particular quality factor level of the planar coil. In some embodiments, the tuner enclosure further includes a shielding case that extends to the base of the substrate, is comprised of a metal material, and is mechanically connected with the substrate.
    Type: Grant
    Filed: May 23, 2004
    Date of Patent: April 15, 2008
    Assignee: RfStream Corporation
    Inventors: Kazunori Okui, Hiroshi Ogasawara, Takatsugu Kamata, Keiichi Fujii, Christopher Li
  • Patent number: 7313218
    Abstract: A radiographic apparatus removes lag-behind parts from radiation detection signals taken from an FPD as X rays are emitted from an X-ray tube, on an assumption that the lag-behind part included in each X-ray detection signal is due to an impulse response formed of a plurality of exponential functions with different attenuation time constants. When a single attenuation time constant and intensity are provisionally set, checking is made whether an attenuation to a noise level of X-ray detection signals occurs in an X-ray non-emission state following an X-ray emission state. When the set attenuation time constant and intensity are found appropriate (OK), the impulse response having the single exponential function is determined valid. Corrected radiation detection signals are obtained by removing the lag-behind parts using the impulse response determined.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: December 25, 2007
    Assignee: Shimadzu Corporation
    Inventors: Shoichi Okamura, Keiichi Fujii, Susumu Adachi, Shinya Hirasawa, Toshinori Yoshimuta, Koichi Tanabe, Shigeya Asai, Akihiro Nishimura
  • Patent number: 7312650
    Abstract: A step-down voltage output circuit preventing: latch-up phenomenon in a load circuit for a period between a power-supply activation and complete start of a charge pump circuit; and rapid change of a substrate potential when a step-down voltage output is changed from ON to OFF. The step-down voltage output circuit has a timer circuit that operates depending on control signals and a timer period; a first N-channel MOS transistor in which a source is connected to a step-down voltage output terminal, a drain is connected to ground, a gate is connected to a power-supply voltage input terminal through a resistance; and a second N-channel MOS transistor in which a source is connected to the step-down voltage output terminal, a drain is connected to the gate of the first N-channel MOS transistor, and a gate is connected to an output terminal of the timer circuit.
    Type: Grant
    Filed: October 18, 2005
    Date of Patent: December 25, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Taku Kobayashi, Keiichi Fujii, Yasunobu Kakumoto, Toshinobu Nagasawa
  • Patent number: 7307465
    Abstract: To provide a step-down voltage output circuit which causes no latch-up phenomenon for the period between activation of a power supply and complete start of operation of a charge pump circuit. The step-down voltage output circuit of the present invention has the charge pump circuit with a first oscillator; a timer circuit in which a timer period is set according to an oscillating frequency of the above-mentioned first oscillator; and an N-channel MOS transistor in which one N-type diffusion layer is connected to an output terminal of the above-mentioned charge pump circuit, the other N-type diffusion layer is connected to ground potential, and a gate electrode is connected to an output terminal of the above-mentioned timer circuit to become conductive for the above-mentioned timer period.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: December 11, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Taku Kobayashi, Keiichi Fujii
  • Publication number: 20070126496
    Abstract: A semiconductor integrated circuit is provided with a signal processing circuit which operates based on a first reference voltage and processes a voice signal, an output amplifier which amplifiers the voice signal, and a pair of BTL output-type output amplifiers which operates based on a second voltage, amplifies the voice signal, and supplies the amplified signal to a speaker. And further, the integrated circuit is provided with a voltage comparator which compares the second reference voltage and a predetermined voltage and a precharging circuit which makes the first reference voltage rapidly reach a stable voltage for a time period during which the second reference voltage reaches the predetermined voltage based on the comparison results from the voltage comparator.
    Type: Application
    Filed: November 29, 2006
    Publication date: June 7, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Akihiro Kawamura, Keiichi Fujii
  • Publication number: 20070096819
    Abstract: A CMOS amplifier according to the present invention includes an input stage, an output stage, a feedforward type idling current control circuit, and an interrupter circuit. The output stage includes a grounded-source push-pull circuit having an output P-channel MOS transistor and an output N-channel MOS transistor. The input stage includes two differential amplifier circuits. The idling current control circuit supplies idling currents to the MOS transistors of the output stage so that the MOS transistors of the output stage perform class AB amplification operations. The interrupter circuit includes a plurality of switches which are off in a stand-by state to stop power supply to the differential amplifier circuits, stop operations of constant current circuits included in the idling current control circuit, and cancel gate-source voltages at the MOS transistors of the output stage.
    Type: Application
    Filed: October 3, 2006
    Publication date: May 3, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Makoto Yamamoto, Keiichi Fujii
  • Patent number: 7203279
    Abstract: In the radiographic apparatus according to this invention, when a radiographic mode designator 16 designates a non-standard radiographic mode, a signal corrector 15 uses defect information stored in one of non-standard image defect information memories 18B–18E for correcting X-ray detection signals outputted from an FPD 2. Since the pixel defect information for non-standard X-ray images is acquired by a pixel defect information converter 19 through a conversion from defect information for standard X-ray images stored in a standard image defect information memory 18A, it is unnecessary to collect output signals for pixel defect information acquisition from the FPD 2 all over again. As a result, abnormal X-ray detection signals due to defects of radiation detecting elements may be corrected promptly, regardless of how the radiation detecting elements are assigned to the pixels in the X-ray images.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: April 10, 2007
    Assignee: Shimadzu Corporation
    Inventors: Keiichi Fujii, Shoichi Okamura, Susumu Adachi, Shinya Hirasawa, Toshinori Yoshimuta, Koichi Tanabe, Shigeya Asai, Akihiro Nishimura
  • Publication number: 20070024347
    Abstract: A semiconductor integrated circuit includes a charge pump circuit for stepping down or stepping up a voltage supplied from a single voltage supply VDD and outputting the voltage, by repeating an operation of charging a flying capacitor C1 and transferring charges stored in the flying capacitor to a storage capacitor C2. During the operation of the charge pump circuit, current supply for charging the flying capacitor is carried out by a current mirror operation. The semiconductor integrated circuit thus obtained by including the charge pump circuit is characterized in that rush current on startup of charge pumping is reduced and that output performance of a DC-CD converter is not impaired.
    Type: Application
    Filed: July 18, 2006
    Publication date: February 1, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Toshinobu Nagasawa, Tetsushi Toyooka, Keiichi Fujii
  • Publication number: 20070013448
    Abstract: While a charge pump activation/deactivation control circuit is outputting a high level signal, MOS transistors for short-circuiting a flying capacitor are off, and the charge pump circuit operates normally. When the charge pump activation/deactivation control circuit outputs a low level signal, the MOS transistors for short-circuiting the flying capacitor are turned on, and the charge pump circuit is deactivated. Consequently, the voltages at the terminals of the flying capacitor are the same and the charge charged therein is discharged. Therefore, when the charge pump circuit is activated again, the initial amount of charge charged to the flying capacitor is zero. Consequently, no large current flows through an output capacitor in the first discharging cycle after the re-activation.
    Type: Application
    Filed: July 12, 2006
    Publication date: January 18, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Satoshi Azuhata, Toshinobu Nagasawa, Tetsushi Toyooka, Keiichi Fujii
  • Publication number: 20070009110
    Abstract: A muting circuit of the present invention includes: an input terminal that receives a control signal for allowing switching between ON and OFF of a mute operation; and a muting transistor connected to the input terminal and an output terminal of the amplifier. The muting transistor is a MOS transistor, and a gate is connected to the input terminal, a drain is connected to the output terminal of the amplifier, and a source is grounded. Consequently, a shot noise due to a DC difference caused when a mute state is switched between ON and OFF can be suppressed.
    Type: Application
    Filed: July 5, 2006
    Publication date: January 11, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yasunobu Kakumoto, Keiichi Fujii
  • Publication number: 20060097785
    Abstract: In a BTL amplifier of the present invention, between first and third transistor parts (10, 11) which are laterally adjacent, directions of semiconductor regions (102, 104, 106) are parallel. Between the first and second transistor parts (10, 12) and the third and fourth transistor parts (12, 13), each which are longitudinally adjacent, directions of semiconductor regions (102, 104, 106) are perpendicular. The first and the third transistor parts (10, 12) are connected to a power supply terminal (1) through a first wire (51). The second and the fourth transistor parts (11, 13) are connected to a ground terminal (2) through a second wire (52). The first and the second transistor parts (10, 11) are connected to a first output terminal (3) through a third wire (53). The third and the fourth transistor parts (12, 13) are connected to a second output terminal (4) through a fourth wire (54).
    Type: Application
    Filed: November 7, 2005
    Publication date: May 11, 2006
    Inventors: Makoto Yamamoto, Keiichi Fujii
  • Publication number: 20060093153
    Abstract: The present invention detects whether the supply voltage applied to the power supply terminal (3) is used for the dynamic speaker or for the piezoelectric speaker by the power supply voltage detection circuit (10), switches the gain of the amplifier circuit (8) in accordance with the detection result by the gain switching circuit (11) so that the same output power is produced for the same input signal in the respective speaker driving, and amplifies the input signal from the input terminal (5) by the amplifier circuit (8) having the gain to drive a speaker (1) that is connected to the output terminals (6, 7).
    Type: Application
    Filed: October 24, 2005
    Publication date: May 4, 2006
    Applicant: Matsushita Electric Industrial Co., LTD.
    Inventors: Makoto Yamamoto, Keiichi Fujii