Patents by Inventor Keiichi Higuchi

Keiichi Higuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11189534
    Abstract: A semiconductor assembly is provided, that includes a semiconductor chip including an upper surface electrode and a lower surface electrode opposite to the upper surface electrode, a metallic wiring plate electrically connected to the semiconductor chip, and a soldering portion that bonds the upper surface electrode of the semiconductor chip to the metallic wiring plate by soldering, the semiconductor chip including a temperature detection portion, an anode wire for the temperature detection portion, and a first insulation layer that blocks the soldering portion and insulates the soldering portion from the anode wire.
    Type: Grant
    Filed: January 26, 2020
    Date of Patent: November 30, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiichi Higuchi
  • Publication number: 20200303267
    Abstract: A semiconductor assembly is provided, that includes a semiconductor chip including an upper surface electrode and a lower surface electrode opposite to the upper surface electrode, a metallic wiring plate electrically connected to the semiconductor chip, and a soldering portion that bonds the upper surface electrode of the semiconductor chip to the metallic wiring plate by soldering, the semiconductor chip including a temperature detection portion, an anode wire for the temperature detection portion, and a first insulation layer that blocks the soldering portion and insulates the soldering portion from the anode wire.
    Type: Application
    Filed: January 26, 2020
    Publication date: September 24, 2020
    Inventor: Keiichi HIGUCHI
  • Patent number: 10784214
    Abstract: A semiconductor module includes: a first lead frame connected to a plurality of semiconductor chips in a first arm circuit; a second lead frame connected to a plurality of semiconductor chips in a second arm circuit; a first main terminal connected to the first lead frame; and a second main terminal connected to the second lead frame, wherein each of the first lead frame and second lead frame has a facing part, a first terminal connection portion connected to the first main terminal is provided at a first end portion of the first lead frame, a second terminal connection portion connected to the second main terminal is provided at a second end portion of the second lead frame, and the first terminal connection portion and second terminal connection portion are arranged on opposite sides when viewed from the facing parts of the first lead frame and second lead frame.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: September 22, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shin Soyano, Hayato Nakano, Keiichi Higuchi, Akihiro Osawa
  • Patent number: 10741550
    Abstract: A reverse-conducting semiconductor device includes a semiconductor chip having a top surface, a first side and a second side orthogonal to the first side in a plan view, in which a plurality of transistor regions and a plurality of diode regions are alternately arranged and an upper-electrode is provided on top surface-sides of the transistor regions and the diode regions; and a wiring member having a flat-plate portion having a rectangular-shape which is metallurgically jointed to the upper-electrode via a joint member above the diode regions. The wiring member has a conductive wall rising from a bending edge of the flat-plate portion in a direction opposite to the upper-electrode, and the bending edge of the flat-plate portion is arranged parallel to the first side.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: August 11, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hayato Nakano, Keiichi Higuchi, Akihiro Osawa
  • Publication number: 20190355718
    Abstract: A reverse-conducting semiconductor device includes a semiconductor chip having a top surface, a first side and a second side orthogonal to the first side in a plan view, in which a plurality of transistor regions and a plurality of diode regions are alternately arranged and an upper-electrode is provided on top surface-sides of the transistor regions and the diode regions; and a wiring member having a flat-plate portion having a rectangular-shape which is metallurgically jointed to the upper-electrode via a joint member above the diode regions. The wiring member has a conductive wall rising from a bending edge of the flat-plate portion in a direction opposite to the upper-electrode, and the bending edge of the flat-plate portion is arranged parallel to the first side.
    Type: Application
    Filed: March 22, 2019
    Publication date: November 21, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hayato Nakano, Keiichi Higuchi, Akihiro Osawa
  • Publication number: 20190157221
    Abstract: A semiconductor module includes: a first lead frame connected to a plurality of semiconductor chips in a first arm circuit; a second lead frame connected to a plurality of semiconductor chips in a second arm circuit; a first main terminal connected to the first lead frame; and a second main terminal connected to the second lead frame, wherein each of the first lead frame and second lead frame has a facing part, a first terminal connection portion connected to the first main terminal is provided at a first end portion of the first lead frame, a second terminal connection portion connected to the second main terminal is provided at a second end portion of the second lead frame, and the first terminal connection portion and second terminal connection portion are arranged on opposite sides when viewed from the facing parts of the first lead frame and second lead frame.
    Type: Application
    Filed: January 29, 2019
    Publication date: May 23, 2019
    Inventors: Shin SOYANO, Hayato NAKANO, Keiichi HIGUCHI, Akihiro OSAWA
  • Patent number: 8933557
    Abstract: A semiconductor module including a cooling unit by which a fine cooling effect is obtained is provided. A plurality of cooling flow paths (21c) which communicate with both of a refrigerant introduction flow path which extends from a refrigerant introduction inlet and a refrigerant discharge flow path which extends to a refrigerant discharge outlet are arranged in parallel with one another in a cooling unit (20). Fins (22) are arranged in each cooling flow path (21c). Semiconductor elements (32) and (33) are arranged over the cooling unit (20) so that the semiconductor elements (32) and (33) are thermally connected to the fins (22). By doing so, a semiconductor module (10) is formed. Heat generated by the semiconductor elements (32) and (33) is conducted to the fins (22) arranged in each cooling flow path (21c) and is removed by a refrigerant which flows along each cooling flow path (21c).
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: January 13, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Hiromichi Gohara, Akira Morozumi, Keiichi Higuchi
  • Publication number: 20120139096
    Abstract: A semiconductor module including a cooling unit by which a fine cooling effect is obtained is provided. A plurality of cooling flow paths (21c) which communicate with both of a refrigerant introduction flow path which extends from a refrigerant introduction inlet and a refrigerant discharge flow path which extends to a refrigerant discharge outlet are arranged in parallel with one another in a cooling unit (20). Fins (22) are arranged in each cooling flow path (21c). Semiconductor elements (32) and (33) are arranged over the cooling unit (20) so that the semiconductor elements (32) and (33) are thermally connected to the fins (22). By doing so, a semiconductor module (10) is formed. Heat generated by the semiconductor elements (32) and (33) is conducted to the fins (22) arranged in each cooling flow path (21c) and is removed by a refrigerant which flows along each cooling flow path (21c).
    Type: Application
    Filed: July 28, 2010
    Publication date: June 7, 2012
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hiromichi Gohara, Akira Morozumi, Keiichi Higuchi
  • Patent number: 7215111
    Abstract: A magnetic motion sensor has: two magnetic sensors aligned in a direction along which changes in a magnetic field shift for detecting an appearance of the changes; a differential means for taking out a differential signal of output signals from these two magnetic sensors; and a timing detection means for generating a pulse, indicating a timing at which the changes in a magnetic field pass through either of the magnetic sensors, when an output signal of the magnetic sensor in question strides over a threshold value, while generating a pulse, indicating a timing at which the changes in a magnetic field pass through in between the magnetic sensors, when the differential signal strides over the threshold value.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: May 8, 2007
    Assignee: Hitachi Cable, Ltd.
    Inventors: Masayoshi Kaneyasu, Kazuhiro Komatsuzaki, Keiichi Higuchi, Takashi Onimoto
  • Publication number: 20060043963
    Abstract: A magnetic motion sensor has: two magnetic sensors aligned in a direction along which changes in a magnetic field shift for detecting an appearance of the changes; a differential means for taking out a differential signal of output signals from these two magnetic sensors; and a timing detection means for generating a pulse, indicating a timing at which the changes in a magnetic field pass through either of the magnetic sensors, when an output signal of the magnetic sensor in question strides over a threshold value, while generating a pulse, indicating a timing at which the changes in a magnetic field pass through in between the magnetic sensors, when the differential signal strides over the threshold value.
    Type: Application
    Filed: August 24, 2005
    Publication date: March 2, 2006
    Inventors: Masayoshi Kaneyasu, Kazuhiro Komatsuzaki, Keiichi Higuchi, Takashi Onimoto
  • Publication number: 20050154066
    Abstract: The object of the present invention is to provide a composition which is effective in retarding or preventing the development of energy decrease, appearance change, etc. of humans and animals due to aging, and is highly safe even with a long period of taking. The present invention relates to an antiaging composition which comprises reduced coenzyme Q as an active ingredient. By feeding mice which develop the aging symptom early (aging-accelerated model mice) with a feed containing reduced coenzyme Q10 for a long period of time, aging process was prevented and retarded. Furthermore, aging-accelerated model mice fed with reduced coenzyme Q10 for a long period of time showed no toxic symptom, thus it was found that the antiaging composition comprising a composition containing said substance can be made into a safe antiaging composition capable of being taken for a long period of time.
    Type: Application
    Filed: January 6, 2005
    Publication date: July 14, 2005
    Inventors: Kenji Fujii, Taizo Kawabe, Hiroshi Kubo, Keiichi Higuchi
  • Patent number: 5903697
    Abstract: An optical waveguide 3 comprises a substrate like a Si substrate having a projection with a flat surface and inclined side surfaces thereon, a buffer layer having a refractive index of n.sub.0 formed on lower surfaces of the substrate, a secondary buffer layer having a refractive index of n.sub.0 formed on the buffer layer, a core waveguide having a refractive index of n.sub.1 formed on the secondary buffer layer and a cladding layer having a refractive index of n.sub.0 covering the core waveguide. The flat surface of the projection 31 is exposed through an opening. The secondary buffer layer controls a transmission loss increase caused by partial thickness differences of the ground buffer layer or scattering by scratches or strains created by the grind.
    Type: Grant
    Filed: July 22, 1997
    Date of Patent: May 11, 1999
    Assignees: Hitachi Ltd., Hitachi Cable, Ltd., Nippon Telegraph and Telephone Corporation
    Inventors: Yasufumi Yamada, Masahiro Yanagisawa, Hiroaki Okano, Keiichi Higuchi, Hisato Uetsuka, Tatsuo Teraoka, Satoshi Aoki, Yasunori Iwafuji
  • Patent number: D774479
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: December 20, 2016
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Shin Soyano, Yoshikazu Takayima, Keiichi Higuchi, Takahiro Koyama
  • Patent number: D814433
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: April 3, 2018
    Assignee: Fuji Electric Co., Ltd
    Inventors: Shin Soyano, Yoshikazu Takamiya, Keiichi Higuchi, Takahiro Koyama
  • Patent number: D827593
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: September 4, 2018
    Assignee: Fuji Electric Co., Ltd
    Inventors: Shin Soyano, Yoshikazu Takamiya, Keiichi Higuchi, Takahiro Koyama