Patents by Inventor Keiichi Ina

Keiichi Ina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130027650
    Abstract: Disclosed is a liquid crystal display device 20 including a display region 11a and a display region 11b. The display region 11a includes pixels 10a provided with, as pixel electrodes, transflective electrodes 15, each including a transmissive electrode 15a that carries out transmissive display, and a reflective electrode 15b that carries out reflective display. The display region 11b includes pixels 10b provided with, as pixel electrodes, transmissive electrodes 16 that carry out transmissive display. The direction in which the long side of the transmissive electrode 15a of the pixel 10a extends is positioned in the same direction in which the long side of the transmissive electrode 16 of the pixel 10b extends. By aligning the long side direction of the transmissive electrode 15a with the long side direction of the transmissive electrode 16, the direction of change in chromaticity in the display region 11a and the direction of change in chromaticity in the display region 11b become the same.
    Type: Application
    Filed: March 16, 2011
    Publication date: January 31, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yuki Kawashima, Keisuke Yoshida, Yasutoshi Tasaka, Ryohji Yayotani, Yoshimizu Moriya, Keiichi Ina
  • Publication number: 20130027649
    Abstract: Each pixel includes: a pixel electrode (1) which is rectangular and a counter electrode (2) which has an opening (5a), the pixel electrode (1) and the counter electrode (2) being provided so as to face each other; and a liquid crystal layer which is provided between the pixel electrode (1) and the counter electrode(2), in plan view, a distance being not less than 10 ?m and not more than 30 ?m between each of short sides of the pixel electrode (1) and the opening (5a).
    Type: Application
    Filed: April 6, 2011
    Publication date: January 31, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yasutoshi Tasaka, Keiichi Ina, Kaori Saitoh
  • Patent number: 8253872
    Abstract: A shield electrode is provided in the vicinity of a pixel electrode and source bus lines. The shield electrode may be provided in the same layer as gate bus lines, or in the same layer as the source bus lines. The shield electrode may be surrounded by an insulating material, or may be connected to a line other than the source bus lines. By providing the shield electrode, it is possible to reduce a source-drain parasitic capacitance between a pixel electrode and a source bus line.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: August 28, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Keiichi Ina, Ichiro Shiraki, Mutsumi Nakajima, Keisuke Yoshida, Shoichi Andou
  • Patent number: 8253669
    Abstract: A first edge (61a) and a second edge (61b) are not uniformly parallel to each other in a direction perpendicular to a first direction (A); a protrusion that is provided on one or both of the first edge (61a) and the second edge (61b), which protrusion protrudes into a slit (62b), is increased in just a direction from one predetermined region on one side of a bisector (C) shared by the first edge (61a) and the second edge (61b) to another region on the other side of the bisector C, which region on one predetermined region and the another region on the other side are regions of the first edge (61a) and the second edge (61b), and all of the protrusion(s) being extended into the slit to reach its maximum in the another region on the other side of the bisector.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: August 28, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Keiichi Ina, Yasutoshi Tasaka
  • Publication number: 20120188212
    Abstract: Provided is a display apparatus wherein a sustain capacitance wire is shared between two rows of pixels to prevent the reduction in aperture ratio and the reduction in yield, and further the capacitive coupling drive can be performed. The display apparatus comprises: pixels arranged in a matrix of n rows and m columns (where n and m represent integers equal to or greater than two); m source lines and n gate lines provided in a grid pattern; and a sustain capacitance unit formed in a boundary area between odd-numbered and even-numbered rows of pixels. The sustain capacitance unit comprises: a sustain capacitance wire shared between the odd-numbered and even-numbered rows of pixels; an insulating film; an opposite electrode used for the odd-numbered row of pixels; and an opposite electrode used for the even-numbered row of pixels.
    Type: Application
    Filed: June 4, 2010
    Publication date: July 26, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Keiichi Ina, Yasuyoshi Kaise, Keisuke Yoshida, Kazuhiro Maeda
  • Publication number: 20120154366
    Abstract: A liquid crystal display device (1) includes a plurality of source bus lines (14), a plurality of gate bus lines (11) that cross the plurality of source bus lines (14), and a plurality of auxiliary capacitance lines (29) that extend in parallel with the gate bus lines (11). The liquid crystal display device (1) also includes a plurality of pixels (30) to (32) that respectively include TFTs (5), pixel electrodes (19), a common electrode (24), and a liquid crystal layer (4) and that are arranged in a matrix so as to correspond to the respective intersections of the gate bus lines (11) and the source bus lines (14). A pixel electrode (19a) for the pixel (31) is disposed in the pixel (30) that is adjacent to the pixel (31), and in a plan view, the gate bus line (11b) disposed in the pixel (31) and the pixel electrode (19a) for the pixel (31) are arranged apart from each other so as not to overlap.
    Type: Application
    Filed: April 30, 2010
    Publication date: June 21, 2012
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Keiichi Ina, Yoshimizu Moriya
  • Publication number: 20110242148
    Abstract: In a display device of the present invention, a total fluctuation calculation portion (23) included in a display control circuit (200) calculates total amounts of potential fluctuations of drive video signals to be applied to video signal lines during one frame period based on external display data signals (DATs). For a pixel formation portion to be provided with a display data signal (DATp) (corresponding to the next display row of the previous frame) received from frame memory (22), a data correction portion (24) performs correction to compensate for impact to be caused by potential fluctuations of an opposite video signal line adjacent but not connected to the pixel formation portion. As a result, the instant delta-arrangement color display device allows horizontal streaks, which are caused by potential fluctuations of opposite video signal lines as mentioned above, to be reduced or eliminated using a simplified configuration.
    Type: Application
    Filed: September 16, 2009
    Publication date: October 6, 2011
    Inventors: Keiichi Ina, Keisuke Yoshida, Takuya Tsuda
  • Publication number: 20100289732
    Abstract: A first edge (61a) and a second edge (61b) are not uniformly parallel to each other in a direction perpendicular to a first direction (A); a protrusion that is provided on one or both of the first edge (61a) and the second edge (61b), which protrusion protrudes into a slit (62b), is increased in just a direction from one predetermined region on one side of a bisector (C) shared by the first edge (61a) and the second edge (61b) to another region on the other side of the bisector C, which region on one predetermined region and the another region on the other side are regions of the first edge (61a) and the second edge (61b), and all of the protrusion(s) being extended into the slit to reach its maximum in the another region on the other side of the bisector.
    Type: Application
    Filed: December 5, 2008
    Publication date: November 18, 2010
    Inventors: Keiichi Ina, Yasutoshi Tasaka
  • Publication number: 20100149468
    Abstract: A liquid crystal display device (10) includes a TFT substrate (11), a CF substrate (12), and a liquid crystal layer (13) interposed therebetween. The liquid crystal layer (13) is made of a liquid crystal material having negative dielectric anisotropy. When no voltage is applied, liquid crystal molecules of the liquid crystal material are oriented substantially vertical to the TFT substrate (11) and the CF substrate (12). A display region of a liquid crystal display panel (14) is formed by a plurality of pixels. Each of the plurality of pixels includes a light reflection display portion (130) and a light transmission display portion (131). Orientation control means (120) for axisymmetrically orienting the liquid crystal molecules when a voltage is applied to the liquid crystal layer (13) is provided in the light reflection display portion (130).
    Type: Application
    Filed: July 7, 2006
    Publication date: June 17, 2010
    Inventors: Keiichi Ina, Keisuke Yoshida
  • Publication number: 20100060806
    Abstract: In one embodiment of the present invention, a liquid crystal display device groups video signal lines SL1 to SLn every 12 video signal lines in order of arrangement and drives video signal lines in each group in a time division manner during a horizontal scanning period. The order of driving video signal lines in each group varies between an even frame and an odd frame, and for each line, in one of the frames, even-numbered video signal lines are driven earlier and in the other one of the frames, odd-numbered video signal lines are driven earlier. The first and last video signal lines to be driven correspond to blue.
    Type: Application
    Filed: March 19, 2008
    Publication date: March 11, 2010
    Inventors: Keiichi Ina, Keisuke Yoshida
  • Patent number: 7605885
    Abstract: A first electrode substrate of the present invention includes a first signal line, a second signal line, a third signal line, a first pixel electrode, a second pixel electrode, and a third pixel electrode. The first signal line, the second signal line and the third signal line extend in a first direction and in parallel to one another. The first pixel electrode is electrically connected to the first signal line. The second pixel electrode is adjacent to the first pixel electrode in the first direction, and is electrically connected to the second signal line. The third pixel electrode is adjacent to the second pixel electrode in the row direction, crossing the first direction, via the second signal line therebetween, and is electrically connected to the third signal line.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: October 20, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Keiichi Ina, Keisuke Yoshida, Ichiro Shiraki, Mutsumi Nakajima
  • Patent number: 7394513
    Abstract: A display device includes: a plurality of signal lines which extend in a zigzag manner in a column direction and to which image signals are supplied, respectively; an insulation film which covers the plurality of signal lines; and a plurality of pixel electrodes which are formed on the insulation film and to which the image signals are input from the plurality of signal lines, respectively. A distance between ones of the pixel electrodes located adjacent to each other in the column direction is equal to or larger than a line width of the signal lines.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: July 1, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shoichi Andou, Mutsumi Nakajima, Ichiro Shiraki, Keisuke Yoshida, Keiichi Ina
  • Publication number: 20080094530
    Abstract: A first electrode substrate of the present invention includes a first signal line, a second signal line, a third signal line, a first pixel electrode, a second pixel electrode, and a third pixel electrode. The first signal line, the second signal line and the third signal line extend in a first direction and in parallel to one another. The first pixel electrode is electrically connected to the first signal line. The second pixel electrode is adjacent to the first pixel electrode in the first direction, and is electrically connected to the second signal line. The third pixel electrode is adjacent to the second pixel electrode in the row direction, crossing the first direction, via the second signal line therebetween, and is electrically connected to the third signal line.
    Type: Application
    Filed: August 15, 2005
    Publication date: April 24, 2008
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Keiichi Ina, Keisuke Yoshida, Ichiro Shiraki, Mutsumi Nakajima
  • Patent number: 7289097
    Abstract: The subject invention discloses a scanning direction control circuit, which includes a bidirectional shift register in which shifting direction is switched in accordance with a switching signal L/R, which is step-upped by a level shifter when having lower amplitude than the driving voltage. The scanning direction control circuit includes a latch circuit between the level shifter and the bidirectional shift register, and a control circuit causes the latch circuit to carry out latching operation after shifting operation of flip-flops constituting the bidirectional shift register is completed in response to output signals of the flip-flops. The control circuit brings the level shifter into active state in a period before, at and after the latching timing, and brings the level shifter into inactive state in the remaining period. With this arrangement, the switching signal L/R can be supplied at a predetermined timing regardless of external input timing thereof, with low power consumption.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: October 30, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Seijirou Gyouten, Sachio Tsujino, Hajime Washio, Eiji Matsuda, Keiichi Ina, Yuhichiroh Murakami, Shunsuke Hayashi, Mamoru Onda
  • Publication number: 20050168665
    Abstract: A shield electrode is provided in the vicinity of a pixel electrode and source bus lines. The shield electrode may be provided in the same layer as gate bus lines, or in the same layer as the source bus lines. The shield electrode may be surrounded by an insulating material, or may be connected to a line other than the source bus lines. By providing the shield electrode, it is possible to reduce a source-drain parasitic capacitance between a pixel electrode and a source bus line.
    Type: Application
    Filed: January 26, 2005
    Publication date: August 4, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Keiichi Ina, Ichiro Shiraki, Mutsumi Nakajima, Keisuke Yoshida, Shoichi Andou
  • Publication number: 20050168678
    Abstract: A display device includes: a plurality of signal lines which extend in a zigzag manner in a column direction and to which image signals are supplied, respectively; an insulation film which covers the plurality of signal lines; and a plurality of pixel electrodes which are formed on the insulation film and to which the image signals are input from the plurality of signal lines, respectively. A distance between ones of the pixel electrodes located adjacent to each other in the column direction is equal to or larger than a line width of the signal lines.
    Type: Application
    Filed: February 2, 2005
    Publication date: August 4, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Shoichi Andou, Mutsumi Nakajima, Ichiro Shiraki, Keisuke Yoshida, Keiichi Ina
  • Publication number: 20040108989
    Abstract: The subject invention discloses a scanning direction control circuit, which includes a bidirectional shift register in which shifting direction is switched in accordance with a switching signal L/R, which is step-upped by a level shifter when having lower amplitude than the driving voltage. The scanning direction control circuit includes a latch circuit between the level shifter and the bidirectional shift register, and a control circuit causes the latch circuit to carry out latching operation after shifting operation of flip-flops constituting the bidirectional shift register is completed in response to output signals of the flip-flops. The control circuit brings the level shifter into active state in a period before, at and after the latching timing, and brings the level shifter into inactive state in the remaining period. With this arrangement, the switching signal L/R can be supplied at a predetermined timing regardless of external input timing thereof, with low power consumption.
    Type: Application
    Filed: November 6, 2003
    Publication date: June 10, 2004
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Seijirou Gyouten, Sachio Tsujino, Hajime Washio, Eiji Matsuda, Keiichi Ina, Yuhichiroh Murakami, Shunsuke Hayashi, Mamoru Onda