Patents by Inventor Keiichi Ina

Keiichi Ina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080094530
    Abstract: A first electrode substrate of the present invention includes a first signal line, a second signal line, a third signal line, a first pixel electrode, a second pixel electrode, and a third pixel electrode. The first signal line, the second signal line and the third signal line extend in a first direction and in parallel to one another. The first pixel electrode is electrically connected to the first signal line. The second pixel electrode is adjacent to the first pixel electrode in the first direction, and is electrically connected to the second signal line. The third pixel electrode is adjacent to the second pixel electrode in the row direction, crossing the first direction, via the second signal line therebetween, and is electrically connected to the third signal line.
    Type: Application
    Filed: August 15, 2005
    Publication date: April 24, 2008
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Keiichi Ina, Keisuke Yoshida, Ichiro Shiraki, Mutsumi Nakajima
  • Patent number: 7289097
    Abstract: The subject invention discloses a scanning direction control circuit, which includes a bidirectional shift register in which shifting direction is switched in accordance with a switching signal L/R, which is step-upped by a level shifter when having lower amplitude than the driving voltage. The scanning direction control circuit includes a latch circuit between the level shifter and the bidirectional shift register, and a control circuit causes the latch circuit to carry out latching operation after shifting operation of flip-flops constituting the bidirectional shift register is completed in response to output signals of the flip-flops. The control circuit brings the level shifter into active state in a period before, at and after the latching timing, and brings the level shifter into inactive state in the remaining period. With this arrangement, the switching signal L/R can be supplied at a predetermined timing regardless of external input timing thereof, with low power consumption.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: October 30, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Seijirou Gyouten, Sachio Tsujino, Hajime Washio, Eiji Matsuda, Keiichi Ina, Yuhichiroh Murakami, Shunsuke Hayashi, Mamoru Onda
  • Publication number: 20050168678
    Abstract: A display device includes: a plurality of signal lines which extend in a zigzag manner in a column direction and to which image signals are supplied, respectively; an insulation film which covers the plurality of signal lines; and a plurality of pixel electrodes which are formed on the insulation film and to which the image signals are input from the plurality of signal lines, respectively. A distance between ones of the pixel electrodes located adjacent to each other in the column direction is equal to or larger than a line width of the signal lines.
    Type: Application
    Filed: February 2, 2005
    Publication date: August 4, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Shoichi Andou, Mutsumi Nakajima, Ichiro Shiraki, Keisuke Yoshida, Keiichi Ina
  • Publication number: 20050168665
    Abstract: A shield electrode is provided in the vicinity of a pixel electrode and source bus lines. The shield electrode may be provided in the same layer as gate bus lines, or in the same layer as the source bus lines. The shield electrode may be surrounded by an insulating material, or may be connected to a line other than the source bus lines. By providing the shield electrode, it is possible to reduce a source-drain parasitic capacitance between a pixel electrode and a source bus line.
    Type: Application
    Filed: January 26, 2005
    Publication date: August 4, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Keiichi Ina, Ichiro Shiraki, Mutsumi Nakajima, Keisuke Yoshida, Shoichi Andou
  • Publication number: 20040108989
    Abstract: The subject invention discloses a scanning direction control circuit, which includes a bidirectional shift register in which shifting direction is switched in accordance with a switching signal L/R, which is step-upped by a level shifter when having lower amplitude than the driving voltage. The scanning direction control circuit includes a latch circuit between the level shifter and the bidirectional shift register, and a control circuit causes the latch circuit to carry out latching operation after shifting operation of flip-flops constituting the bidirectional shift register is completed in response to output signals of the flip-flops. The control circuit brings the level shifter into active state in a period before, at and after the latching timing, and brings the level shifter into inactive state in the remaining period. With this arrangement, the switching signal L/R can be supplied at a predetermined timing regardless of external input timing thereof, with low power consumption.
    Type: Application
    Filed: November 6, 2003
    Publication date: June 10, 2004
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Seijirou Gyouten, Sachio Tsujino, Hajime Washio, Eiji Matsuda, Keiichi Ina, Yuhichiroh Murakami, Shunsuke Hayashi, Mamoru Onda