Abstract: A semiconductor device includes a latch including a first-node and a second-node. A first-transistor is between the first-node and a first-BL and has a gate connected to a WL. A second-transistor is between the second-node and a second-BL and has a gate connected to the WL. A power-supply line is connected to the latch. A third-transistor is connected between the first-node and a reference-voltage source. A fourth-transistor is between the second-node and the reference-voltage source and has a gate connected to the reference-voltage source. A signal line is connected to a gate of the third-transistor. In a first-mode, the power-supply line supplies a first-voltage to the latch and the signal line brings the third-transistor to a non-conduction state. In a second-mode, the power-supply line supplies a second-voltage to the latch and the signal line brings the third-transistor to a conduction state and connects the first-node to the reference-voltage source.

Abstract: According to one embodiment, a semiconductor device includes a first chip and a second chip. The first chip includes a first surface including a first region at an end, the first region in which a first electrode is provided. The second chip includes a second surface including a second region at an end, the second region in which a second electrode is provided. A third region of the first surface of the first chip, other than the first region, and a fourth region of the second surface of the second chip, other than the second region, are bonded in a state that the third region and the fourth region are at least partially opposed to each other, such that the first electrode of the first chip and the second electrode of the second chip are exposed in opposite directions to each other.

Abstract: A semiconductor memory device includes a memory cell, a pair of local bit lines connected to the memory cell, first and second transistors, one end of the current channel of each connected to a power supply and the other end of the current channel of each connected to one of the local bit lines, third and fourth transistors, one end of the current channel of each connected to one of the local bit lines, the other end of the current channel of each connected to one of the global bit lines, fifth and sixth transistors, one end of the current channel of each connected to one of the global bit lines and the other end of the current channel of which connected to the power supply. The device further includes a control unit configured to control the transistors.

Abstract: According to one embodiment, there is provided a semiconductor memory device including a memory cell. The memory cell includes a first driving transistor, a first load transistor, a first read transfer transistor, a first write transfer transistor, a second driving transistor, a second load transistor, a second read transfer transistor, a second write transfer transistor, and one or more variable resistance elements. The one or more variable resistance elements has resistance that changes depending on a direction of a bias applied to both terminals. The one or more variable resistance elements are arranged in at least one of a portion between a first storage node and a first write transfer transistor and a portion between a second storage node and a second write transfer transistor.

Abstract: A semiconductor memory device includes a memory cell, a pair of local bit lines connected to the memory cell, first and second transistors, one end of the current channel of each connected to a power supply and the other end of the current channel of each connected to one of the local bit lines, third and fourth transistors, one end of the current channel of each connected to one of the local bit lines, the other end of the current channel of each connected to one of the global bit lines, fifth and sixth transistors, one end of the current channel of each connected to one of the global bit lines and the other end of the current channel of which connected to the power supply. The device further includes a control unit configured to control the transistors.

Abstract: According to one embodiment, there is provided a semiconductor memory device including a memory cell. The memory cell includes a first driving transistor, a first load transistor, a first read transfer transistor, a first write transfer transistor, a second driving transistor, a second load transistor, a second read transfer transistor, a second write transfer transistor, and one or more variable resistance elements. The one or more variable resistance elements has resistance that changes depending on a direction of a bias applied to both terminals. The one or more variable resistance elements are arranged in at least one of a portion between a first storage node and a first write transfer transistor and a portion between a second storage node and a second write transfer transistor.

Abstract: According to one embodiment, there is provided a semiconductor memory device including a memory cell. The memory cell includes a first driving transistor, a first load transistor, a first read transfer transistor, a first write transfer transistor, a second driving transistor, a second load transistor, a second read transfer transistor, a second write transfer transistor, and one or more variable resistance elements. The one or more variable resistance elements has resistance that changes depending on a direction of a bias applied to both terminals. The one or more variable resistance elements are arranged in at least one of a portion between a first storage node and a first write transfer transistor and a portion between a second storage node and a second write transfer transistor.

Abstract: According to one embodiment, there is provided a semiconductor memory device including a memory cell. The memory cell includes a first driving transistor, a first load transistor, a first read transfer transistor, a first write transfer transistor, a second driving transistor, a second load transistor, a second read transfer transistor, a second write transfer transistor, and one or more variable resistance elements. The one or more variable resistance elements has resistance that changes depending on a direction of a bias applied to both terminals. The one or more variable resistance elements are arranged in at least one of a portion between a first storage node and a first write transfer transistor and a portion between a second storage node and a second write transfer transistor.

Abstract: According to the embodiments, a semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, and a row selector that multiply-selects the word lines, wherein the semiconductor storage device satisfies Ncell/NWL?(4×Cbl×VDD)/(Icell×Tcyc), where Ncell is number of memory cells connected to each of the bit lines, NWL is a unit of number of word lines multiply-selected by the row selector, Cbl is a value obtained by dividing a capacitance of the bit line by Ncell, VDD is a power supply voltage, Tcyc is an operating frequency of each of the memory cells, and Icell is a target value of current read out via each of the bit lines.

Abstract: A channel layer is deposited on a first impurity layer, a second impurity layer is deposited on the channel layer, a gate electrode is placed to surround a circumference of the channel layer with a gate insulating film interposed therebetween, a spin-injection magnetization-reversal element is deposited on the second impurity layer, a bit line is placed on the spin-injection magnetization-reversal element, and a word line is placed on the bit line to be electrically connected to the gate electrode.

Abstract: The semiconductor memory device executes, in address units, operation for inverting data stored in a memory cell designated by an internal address and writing the data in the memory cell and increments the internal address every time inversion writing operation for the memory cell is executed.

Abstract: In one embodiment, a semiconductor storage device includes a memory cell, a sense amplifier, a bit line, a pre-charge circuit, and a power-supply-voltage switching circuit. The memory cell is configured to store data. The sense amplifier is configured to amplify a signal from the memory cell. The bit line is configured to transmit the signal from the memory cell to the sense amplifier. The pre-charge circuit is configured to pre-charge the bit line. The power-supply-voltage switching circuit is configured to switch a voltage of a power supply and to actuate the sense amplifier after the bit line is pre-charged by the pre-charge circuit, wherein the power-supply-voltage switching circuit is configured to switch the voltage of the power supply to be larger than a voltage during the pre-charge by the pre-charge circuit.

Abstract: An SRAM cell includes one pair of drive transistors, one pair of load transistors, one pair of write access transistors, one pair of read drive transistors, and one pair of access transistors. A voltage source potential is supplied to drains of the read drive transistors.

Abstract: According to the embodiments, a semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, and a row selector that multiply-selects the word lines, wherein the semiconductor storage device satisfies Ncell/NWL?(4×Cbl×VDD)/(Icell×Tcyc), where Ncell is number of memory cells connected to each of the bit lines, NWL is a unit of number of word lines multiply-selected by the row selector, Cbl is a value obtained by dividing a capacitance of the bit line by Ncell, VDD is a power supply voltage, Tcyc is an operating frequency of each of the memory cells, and Icell is a target value of current read out via each of the bit lines.

Abstract: A semiconductor memory device includes a first write bit line, a second write bit line, a write word line, a first read bit line, a read word line, and a memory cell array including a plurality of memory cells, and arranged the plurality of memory cells in a matrix fashion, wherein the memory cells including a first inverter including a first PMOS transistor and a first NMOS transistor, a second inverter including a second PMOS transistor, and a second NMOS transistor, and including an input terminal and an output terminal connected to an output terminal and an input terminal of the first inverter, respectively, a first write transfer transistor connected between a first write bit line and the output terminal of the first inverter, and including a gate connected to a write word line, a second write transfer transistor connected between a second write bit line and the output terminal of the second inverter, and including a gate connected to the write word line, a first read driver transistor including a gate c

Abstract: A semiconductor memory device comprises a word line; a bit line crossing the word line; a memory cell connected to intersection of the word line and the bit line; and a sense circuit connected to sense node coupled to the bit line. The sense circuit includes a first transistor of the first conduction type having a gate connected to the sense node, a second transistor of the second conduction type having a source connected to a first power supply, a drain connected to the sense node, and a gate connected to the drain of the first transistor, a third transistor having a source connected to the first power supply, a drain connected to the drain of the first transistor, and a gate connected to a control signal line, and a fourth transistor having a source connected to a second power supply, a drain connected to the source of the first transistor, and a gate connected to the control signal line. The sense circuit is activated with a control signal given to the control signal line.

Abstract: An integrated circuit device includes a plurality of memory circuits, a memory hibernation state control circuit to bring the memory circuits into a hibernation state in response to an external command, a state controller which indicates an interrupt in a memory circuit in a hibernation state, and a plurality of partial error checking and correcting (ECC) code generating circuits which are provided for the memory circuits, respectively, to code hold data of an address of a memory circuit in a hibernation state in accordance with a rule of a Hamming code determinant by an interrupt in the memory circuit in the hibernation state. The integrated circuit device further includes a code storage memory which obtains ECC code data corresponding to all of the hold data based on partial ECC codes coded by the partial ECC code generating circuit and stores the ECC code data in a corresponding address.

Abstract: A semiconductor memory device comprises a plurality of cell arrays, each cell array containing a plurality of word lines, a plurality of bit lines crossing the word lines, and memory cells connected at intersections of the word lines and bit lines, the cell arrays arranged along the bit line; a plurality of bit line gates provided between the cell arrays and each operative to establish a connection between the bit lines in adjacent cell arrays; and a controlling circuit operative to form a data transfer path via the connection between the bit lines formed through the bit line gate when the controlling circuit accesses to the memory cell.

Abstract: The semiconductor memory device executes, in address units, operation for inverting data stored in a memory cell designated by an internal address and writing the data in the memory cell and increments the internal address every time inversion writing operation for the memory cell is executed.

Abstract: An SRAM cell includes one pair of drive transistors, one pair of load transistors, one pair of write access transistors, one pair of read drive transistors, and one pair of access transistors. A voltage source potential is supplied to drains of the read drive transistors.