Abstract: After a bit line is pre-charged by a pre-charge circuit that pre-charges the bit line, the voltage of a power supply for actuating a sense amplifier, which amplifies a signal read out from a memory cell, is switched.

Abstract: A semiconductor memory device includes a first write bit line, a second write bit line, a write word line, a first read bit line, a read word line, and a memory cell array including a plurality of memory cells, and arranged the plurality of memory cells in a matrix fashion, wherein the memory cells including a first inverter including a first PMOS transistor and a first NMOS transistor, a second inverter including a second PMOS transistor, and a second NMOS transistor, and including an input terminal and an output terminal connected to an output terminal and an input terminal of the first inverter, respectively, a first write transfer transistor connected between a first write bit line and the output terminal of the first inverter, and including a gate connected to a write word line, a second write transfer transistor connected between a second write bit line and the output terminal of the second inverter, and including a gate connected to the write word line, a first read driver transistor including a gate c

Abstract: A channel layer is deposited on a first impurity layer, a second impurity layer is deposited on the channel layer, a gate electrode is placed to surround a circumference of the channel layer with a gate insulating film interposed therebetween, a spin-injection magnetization-reversal element is deposited on the second impurity layer, a bit line is placed on the spin-injection magnetization-reversal element, and a word line is placed on the bit line to be electrically connected to the gate electrode.

Abstract: A semiconductor memory device includes a first block and a second block adjacent to each other in a column direction, each block including first and second memory cell arrays each including a plurality of local bit lines and a local sense amplifier shared by the first and second memory cell arrays, a plurality of global bit lines shared by the first block and the second block, a global sense amplifier configured to sense data transferred to the global bit lines, first and second replica cell groups provided in the first and second blocks, first and second replica bit lines connected to the first and second replica cell groups, an activation circuit connected to each replica bit line, and configured to activate the local sense amplifier, an edge cell group surrounding the first block and the second block, and a contact region surrounding the edge cell group.

Abstract: A semiconductor memory device includes a plurality of memory cell columns each having a plurality of memory cells, each memory cell including being a static type, a plurality of local bit lines connected to the memory cell columns, a global bit line connected to the local bit lines via a plurality of sense amplifiers, a measurement terminal to which a measurement voltage is applied in a cell current measurement mode, and a plurality of switching circuits provided to correspond to the local bit lines, and configured to electrically connect the measurement terminal and one of the local bit lines in the cell current measurement mode.

Abstract: A programming method of a MOS electric fuse including preparing, as a fuse element, a MOS transistor which has a first impurity region and a second impurity region, both of a second conductivity type, formed to face with each other on an upper surface of a well of a first conductivity type on a semiconductor substrate, a gate dielectric film formed on the upper surface of the well at least between the first impurity region and the second impurity region, and a gate electrode formed through the gate dielectric film on the upper surface of the well held between the first impurity region and the second impurity region, and applying a first voltage to the gate electrode, and a second voltage different from the first voltage to the first impurity region, and short-circuiting the gate dielectric film only between the gate electrode and the first impurity region.

Abstract: A semiconductor memory device comprises a plurality of cell arrays, each cell array containing a plurality of word lines, a plurality of bit lines crossing the word lines, and memory cells connected at intersections of the word lines and bit lines, the cell arrays arranged along the bit line; a plurality of bit line gates provided between the cell arrays and each operative to establish a connection between the bit lines in adjacent cell arrays; and a controlling circuit operative to form a data transfer path via the connection between the bit lines formed through the bit line gate when the controlling circuit accesses to the memory cell.

Abstract: A semiconductor memory device comprises a word line; a bit line crossing the word line; a memory cell connected to intersection of the word line and the bit line; and a sense circuit connected to sense node coupled to the bit line. The sense circuit includes a first transistor of the first conduction type having a gate connected to the sense node, a second transistor of the second conduction type having a source connected to a first power supply, a drain connected to the sense node, and a gate connected to the drain of the first transistor, a third transistor having a source connected to the first power supply, a drain connected to the drain of the first transistor, and a gate connected to a control signal line, and a fourth transistor having a source connected to a second power supply, a drain connected to the source of the first transistor, and a gate connected to the control signal line. The sense circuit is activated with a control signal given to the control signal line.

Abstract: A semiconductor memory device includes a first inverter circuit and a second inverter circuit, a first transfer gate which is connected between a first power node of the first inverter circuit and a first bit line, a second transfer gate which is connected between a second power node of the second inverter circuit and a second bit line, a first word line connected to gate terminals of the first transfer gate and the second transfer gate, a first read transistor connected between the first power node and a second word line, a second read transistor connected between the second power node and the second word line, and an application circuit which is connected to the second word line, and applies a read voltage to the second word line in reading data.

Abstract: A semiconductor memory device includes a first block and a second block adjacent to each other in a column direction, each block including first and second memory cell arrays each including a plurality of local bit lines and a local sense amplifier shared by the first and second memory cell arrays, a plurality of global bit lines shared by the first block and the second block, a global sense amplifier configured to sense data transferred to the global bit lines, first and second replica cell groups provided in the first and second blocks, first and second replica bit lines connected to the first and second replica cell groups, an activation circuit connected to each replica bit line, and configured to activate the local sense amplifier, an edge cell group surrounding the first block and the second block, and a contact region surrounding the edge cell group.

Abstract: A semiconductor device is disclosed which includes a data memory which stores data and a code memory which stores an ECC code corresponding to the data. The semiconductor device includes an ECC unit which outputs, to the data memory as the data, a test pattern required to test the data memory, and which generates, from the test pattern, code information having an error checking function, and outputs the code information to the code memory as the ECC code.

Abstract: A semiconductor memory device includes a plurality of memory cell columns each having a plurality of memory cells, each memory cell including being a static type, a plurality of local bit lines connected to the memory cell columns, a global bit line connected to the local bit lines via a plurality of sense amplifiers, a measurement terminal to which a measurement voltage is applied in a cell current measurement mode, and a plurality of switching circuits provided to correspond to the local bit lines, and configured to electrically connect the measurement terminal and one of the local bit lines in the cell current measurement mode.

Abstract: An integrated circuit device includes a plurality of memory circuits, a memory hibernation state control circuit to bring the memory circuits into a hibernation state in response to an external command, a state controller which indicates an interrupt in a memory circuit in a hibernation state, and a plurality of partial ECC code generating circuits which are provided for the memory circuits, respectively, to code hold data of an address of a memory circuit in a hibernation state in accordance with a rule of a Hamming code determinant by an interrupt in the memory circuit in the hibernation state. The integrated circuit device further includes a code storage memory which obtains ECC code data corresponding to all of the hold data based on partial ECC codes coded by the partial ECC code generating circuit and stores the ECC code data in a corresponding address.

Abstract: A semiconductor memory device includes a first inverter circuit and a second inverter circuit, a first transfer gate which is connected between a first power node of the first inverter circuit and a first bit line, a second transfer gate which is connected between a second power node of the second inverter circuit and a second bit line, a first word line connected to gate terminals of the first transfer gate and the second transfer gate, a first read transistor connected between the first power node and a second word line, a second read transistor connected between the second power node and the second word line, and an application circuit which is connected to the second word line, and applies a read voltage to the second word line in reading data.

Abstract: A programming method of a MOS electric fuse including preparing, as a fuse element, a MOS transistor which has a first impurity region and a second impurity region, both of a second conductivity type, formed to face with each other on an upper surface of a well of a first conductivity type on a semiconductor substrate, a gate dielectric film formed on the upper surface of the well at least between the first impurity region and the second impurity region, and a gate electrode formed through the gate dielectric film on the upper surface of the well held between the first impurity region and the second impurity region, and applying a first voltage to the gate electrode, and a second voltage different from the first voltage to the first impurity region, and short-circuiting the gate dielectric film only between the gate electrode and the first impurity region.

Abstract: A plurality of MOS type circuits is provided, and are connected in a multistage manner. A first transistor is inserted between a power source voltage VDD and a power supply node of each of MOS type circuits at an odd numbered stage. A second transistor is inserted between the power source voltage VDD and a power supply node of each of MOS type circuits at an even numbered stage. When the plurality of MOS type circuits are established in a standby state, a control circuit first controls to make a second transistor conductive, and then make a first transistor conductive when the plurality of MOS type circuits, each of which is established in a standby state, are recovered from the standby state to an active state.

Abstract: A semiconductor memory comprises, a data memory having a plurality of memory regions to store data at addresses specified, a code memory having the same address space as the data memory to store error correction codes, an error correction code control circuit including an error correction code generation circuit, a syndrome generation circuit and an error correction code decoding circuit, generating an error correction code for correcting data before the data is written back into the memory region, and comparing the generated error correction code with corresponding error correction code, thereby to determine whether the data is erroneous, and an error correction code function invalidity control circuit invalidating an error correction function of the error correction code control circuit when the memory regions are accessed first after power application.

Abstract: A first P-channel transistor is connected between a gate of an N-channel transistor constituting a last-stage buffer circuit and an output of a prebuffer circuit. A second P-channel transistor is connected between the power supply node and a gate of a P-channel transistor constituting a last-stage buffer circuit. A first N-channel transistor is connected between an N-channel transistor constituting the prebuffer circuit and the ground potential supply node. A second N-channel transistor is connected between the power supply node and a P-channel transistor constituting the main buffer circuit.

Abstract: A first P-channel transistor is connected between a gate of an N-channel transistor constituting a last-stage buffer circuit and an output of a prebuffer circuit. A second P-channel transistor is connected between the power supply node and a gate of a P-channel transistor constituting a last-stage buffer circuit. A first N-channel transistor is connected between an N-channel transistor constituting the prebuffer circuit and the ground potential supply node. A second N-channel transistor is connected between the power supply node and a P-channel transistor constituting the main buffer circuit.

Abstract: A plurality of MOS type circuits is provided, and are connected in a multistage manner. A first transistor is inserted between a power source voltage VDD and a power supply node of each of MOS type circuits at an odd numbered stage. A second transistor is inserted between the power source voltage VDD and a power supply node of each of MOS type circuits at an even numbered stage. When the plurality of MOS type circuits are established in a standby state, a control circuit first controls to make a second transistor conductive, and then make a first transistor conductive when the plurality of MOS type circuits, each of which is established in a standby state, are recovered from the standby state to an active state.