Patents by Inventor Keiichi Nakazawa

Keiichi Nakazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250151448
    Abstract: An imaging element according to an embodiment of the present disclosure includes: a first substrate, a second substrate, and a third substrate that are stacked in this order. The first substrate including a sensor pixel that performs photoelectric conversion and the second substrate including a readout circuit are electrically coupled to each other by a first through wiring line provided in an interlayer insulating film. The second substrate and the third substrate including a logic circuit are electrically coupled to each other by a junction between pad electrodes or a second through wiring line penetrating through a semiconductor substrate.
    Type: Application
    Filed: December 30, 2024
    Publication date: May 8, 2025
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Keiichi NAKAZAWA, Yoshiaki KITANO, Hirofumi Yamashita, Minoru ISHIDA
  • Publication number: 20250133845
    Abstract: A photodetector according to one embodiment of the present disclosure includes a semiconductor layer, a plurality of pixels including a first pixel including a photoelectric conversion element provided in the semiconductor layer, and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer. The first pixel includes a transistor provided on a side of a first surface of the semiconductor layer, a first semiconductor region having a first conductivity type, which is provided on the side of the first surface of the semiconductor layer, and a first contact that is electrically coupled to the first semiconductor region. The first semiconductor region is in contact with the transistor.
    Type: Application
    Filed: February 14, 2023
    Publication date: April 24, 2025
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Kazuhiro YONEDA, Akira DAICHO, Hiroshi FUKUNAGA, Yusuke OTAKE, Suzunori ENDO, Keiichi NAKAZAWA, Hidetoshi OISHI
  • Patent number: 12266675
    Abstract: An imaging element according to an embodiment of the present disclosure includes: a first substrate, a second substrate, and a third substrate that are stacked in this order. The first substrate including a sensor pixel that performs photoelectric conversion and the second substrate including a readout circuit are electrically coupled to each other by a first through wiring line provided in an interlayer insulating film. The second substrate and the third substrate including a logic circuit are electrically coupled to each other by a junction between pad electrodes or a second through wiring line penetrating through a semiconductor substrate.
    Type: Grant
    Filed: September 14, 2023
    Date of Patent: April 1, 2025
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Keiichi Nakazawa, Yoshiaki Kitano, Hirofumi Yamashita, Minoru Ishida
  • Publication number: 20250098351
    Abstract: There is provided a solid-state imaging device including: a first semiconductor layer including a photoelectric converter and an electric charge accumulation section for each pixel, the electric charge accumulation section in which a signal electric charge generated in the photoelectric converter is accumulated; a pixel separation section that is provided in the first semiconductor layer, and partitions a plurality of the pixels from each other; a second semiconductor layer that is provided with a pixel transistor and is stacked on the first semiconductor layer, the pixel transistor that reads the signal electric charge of the electric charge accumulation section; and a first shared coupling section that is provided between the second semiconductor layer and the first semiconductor layer, and is provided to straddle the pixel separation section and is electrically coupled to a plurality of the electric charge accumulation sections.
    Type: Application
    Filed: September 25, 2024
    Publication date: March 20, 2025
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Keiichi NAKAZAWA, Koichiro ZAITSU, Nobutoshi FUJII, Yohei HIURA, Shigetaka MORI, Shintaro OKAMOTO, Keiji OHSHIMA, Shuji MANDA, Junpei YAMAMOTO, Yui YUGA, Shinichi MIYAKE, Tomoki KAMBE, Ryo OGATA, Tatsuki MIYAJI, Shinji NAKAGAWA, Hirofumi YAMASHITA, Yasushi HAMAMOTO, Naohiko KIMIZUKA
  • Patent number: 12136641
    Abstract: To realize miniaturization of a pixel, reduction in noise, and high quantum efficiency, and to improve short-wavelength sensitivity while suppressing inter-pixel interference and variations for each pixel. According to the present disclosure, there is provided an imaging device including: a first semiconductor layer formed in a semiconductor substrate; a second semiconductor layer of a conductivity type opposite to a conductivity type of the first semiconductor layer formed on the first semiconductor layer; a pixel separation unit which defines a pixel region including the first semiconductor layer and the second semiconductor layer; a first electrode which is connected to the first semiconductor layer from one surface side of the semiconductor substrate; and a second electrode which is connected to the second semiconductor layer from a light irradiation surface side that is the other surface of the semiconductor substrate, and is formed to correspond to a position of the pixel separation unit.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: November 5, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Jun Ogi, Yoshiaki Tashiro, Takahiro Toyoshima, Yorito Sakano, Yusuke Oike, Hongbo Zhu, Keiichi Nakazawa, Yukari Takeya, Atsushi Okuyama, Yasufumi Miyoshi, Ryosuke Matsumoto, Atsushi Horiuchi
  • Patent number: 12136640
    Abstract: There is provided a solid-state imaging device including: a first semiconductor layer including a photoelectric converter and an electric charge accumulation section for each pixel, the electric charge accumulation section in which a signal electric charge generated in the photoelectric converter is accumulated; a pixel separation section that is provided in the first semiconductor layer, and partitions a plurality of the pixels from each other; a second semiconductor layer that is provided with a pixel transistor and is stacked on the first semiconductor layer, the pixel transistor that reads the signal electric charge of the electric charge accumulation section; and a first shared coupling section that is provided between the second semiconductor layer and the first semiconductor layer, and is provided to straddle the pixel separation section and is electrically coupled to a plurality of the electric charge accumulation sections.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: November 5, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Keiichi Nakazawa, Koichiro Zaitsu, Nobutoshi Fujii, Yohei Hiura, Shigetaka Mori, Shintaro Okamoto, Keiji Ohshima, Shuji Manda, Junpei Yamamoto, Yui Yuga, Shinichi Miyake, Tomoki Kambe, Ryo Ogata, Tatsuki Miyaji, Shinji Nakagawa, Hirofumi Yamashita, Yasushi Hamamoto, Naohiko Kimizuka
  • Publication number: 20240313030
    Abstract: A first light-receiving element of an embodiment of the disclosure includes: a semiconductor substrate including a photoelectric conversion region; a first first electrically-conductive region provided at a first surface interface of the semiconductor substrate and coupled to a first electrode; a second first electrically-conductive region provided around the first first electrically-conductive region and coupled to a second electrode, at the first surface interface; a third first electrically-conductive region in an electrically floating state provided around the second first electrically-conductive region, at the first surface interface; a first second electrically-conductive region having a different electrically-conductive type between the first first electrically-conductive region and the second first electrically-conductive region, at the first surface interface; and a fourth first electrically-conductive region provided at least between the first first electrically conductive region and the first secon
    Type: Application
    Filed: March 25, 2022
    Publication date: September 19, 2024
    Applicants: SONY SEMICONDUCTOR SOLUTIONS CORPORATION, RIKEN
    Inventors: Takahiro KAWAMURA, Hiroki TOJINBARA, Takaki HATSUI, Shinichi YOSHIDA, Keiichi NAKAZAWA, Hikaru IWATA, Kazunobu OTA, Takuya MARUYAMA, Hiroaki ISHIWATA, Chihiro ARAI, Atsuhiro ANDO, Toru SHIRAKATA, Hisahiro ANSAI, Satoe MIYATA, Ryu KAMIBABA, Yusuke UESAKA, Yukari TAKEYA
  • Publication number: 20240178254
    Abstract: Provided is a light-receiving element capable of reducing a decrease in a photodiode region of a pixel. The light-receiving element includes a pixel array unit in which a plurality of pixels is disposed in an array, the pixels being capable of generating an electrical signal according to light incident from outside. Each of the plurality of pixels includes a photoelectric conversion region of a first conductivity type, the photoelectric conversion region photoelectrically converting the light incident, an inter-pixel separation part that defines an outer edge shape of the pixels, and insulates and separates adjacent pixels, and a pinning region of a second conductivity type, the pinning region being formed between the photoelectric conversion region and a sidewall of the inter-pixel separation part. The plurality of pixels is disposed in an array so as to form a honeycomb structure in which corner parts where a plurality of sides intersects are obtuse angles in plan view.
    Type: Application
    Filed: January 27, 2022
    Publication date: May 30, 2024
    Inventor: KEIICHI NAKAZAWA
  • Publication number: 20240006448
    Abstract: Provided is an imaging device including: a first semiconductor substrate provided with a photoelectric conversion element, a second semiconductor substrate stacked on the first semiconductor substrate with an interlayer insulating film interposed therebetween and provided with a pixel circuit that reads out charges generated in the photoelectric conversion element as a pixel signal, and a via that penetrates the interlayer insulating film and electrically connects a first surface of the first semiconductor substrate facing the second semiconductor substrate and at least a part of a second surface of the second semiconductor substrate facing the first surface.
    Type: Application
    Filed: October 11, 2021
    Publication date: January 4, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takeya MOCHIZUKI, Keiichi NAKAZAWA, Shinichi YOSHIDA, Kenya NISHIO, Nobutoshi FUJII, Suguru SAITO, Masaki OKAMOTO, Ryosuke KAMATANI, Yuichi YAMAMOTO, Kazutaka IZUKASHI, Yuki MIYANAMI, Hirotaka YOSHIOKA, Hiroshi HORIKOSHI, Takuya KUROTORI, Shunsuke FURUSE, Takayoshi HONDA
  • Publication number: 20230420478
    Abstract: An imaging element according to an embodiment of the present disclosure includes: a first substrate, a second substrate, and a third substrate that are stacked in this order. The first substrate including a sensor pixel that performs photoelectric conversion and the second substrate including a readout circuit are electrically coupled to each other by a first through wiring line provided in an interlayer insulating film. The second substrate and the third substrate including a logic circuit are electrically coupled to each other by a junction between pad electrodes or a second through wiring line penetrating through a semiconductor substrate.
    Type: Application
    Filed: September 14, 2023
    Publication date: December 28, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Keiichi NAKAZAWA, Yoshiaki KITANO, Hirofumi YAMASHITA, Minoru ISHIDA
  • Publication number: 20230411429
    Abstract: An imaging device according to an embodiment of the present disclosure includes: a first semiconductor layer including, for each pixel, a photoelectric conversion section and a charge accumulation section that accumulates signal charge generated in the photoelectric conversion section; a second semiconductor layer stacked on the first semiconductor layer and having a first surface provided with a pixel transistor, in which the pixel transistor has a three-dimensional structure and reads the signal charge from the charge accumulation section; and a through-wiring line that directly couples the charge accumulation section and a gate electrode of the pixel transistor to each other.
    Type: Application
    Filed: October 20, 2021
    Publication date: December 21, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Keiichi NAKAZAWA, Takashi KOJIMA, Shinichi IMAI, Tokihisa KANEGUCHI, Koichiro SAGA, Kai TOKUHIRO, Takaaki HIRANO
  • Patent number: 11798972
    Abstract: An imaging element according to an embodiment of the present disclosure includes: a first substrate, a second substrate, and a third substrate that are stacked in this order. The first substrate including a sensor pixel that performs photoelectric conversion and the second substrate including a readout circuit are electrically coupled to each other by a first through wiring line provided in an interlayer insulating film. The second substrate and the third substrate including a logic circuit are electrically coupled to each other by a junction between pad electrodes or a second through wiring line penetrating through a semiconductor substrate.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: October 24, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Keiichi Nakazawa, Yoshiaki Kitano, Hirofumi Yamashita, Minoru Ishida
  • Publication number: 20230154964
    Abstract: An imaging element according to an embodiment of the present disclosure includes: a first substrate, a second substrate, and a third substrate that are stacked in this order. The first substrate including a sensor pixel that performs photoelectric conversion and the second substrate including a readout circuit are electrically coupled to each other by a first through wiring line provided in an interlayer insulating film. The second substrate and the third substrate including a logic circuit are electrically coupled to each other by a junction between pad electrodes or a second through wiring line penetrating through a semiconductor substrate.
    Type: Application
    Filed: December 12, 2022
    Publication date: May 18, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Keiichi NAKAZAWA, Yoshiaki KITANO, Hirofumi YAMASHITA, Minoru ISHIDA
  • Patent number: 11600651
    Abstract: An imaging element according to an embodiment of the present disclosure includes: a first substrate, a second substrate, and a third substrate that are stacked in this order. The first substrate including a sensor pixel that performs photoelectric conversion and the second substrate including a readout circuit are electrically coupled to each other by a first through wiring line provided in an interlayer insulating film. The second substrate and the third substrate including a logic circuit are electrically coupled to each other by a junction between pad electrodes or a second through wiring line penetrating through a semiconductor substrate.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: March 7, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Keiichi Nakazawa, Yoshiaki Kitano, Hirofumi Yamashita, Minoru Ishida
  • Publication number: 20220344386
    Abstract: To realize miniaturization of a pixel, reduction in noise, and high quantum efficiency, and to improve short-wavelength sensitivity while suppressing inter-pixel interference and variations for each pixel. According to the present disclosure, there is provided an imaging device including: a first semiconductor layer formed in a semiconductor substrate; a second semiconductor layer of a conductivity type opposite to a conductivity type of the first semiconductor layer formed on the first semiconductor layer; a pixel separation unit which defines a pixel region including the first semiconductor layer and the second semiconductor layer; a first electrode which is connected to the first semiconductor layer from one surface side of the semiconductor substrate; and a second electrode which is connected to the second semiconductor layer from a light irradiation surface side that is the other surface of the semiconductor substrate, and is formed to correspond to a position of the pixel separation unit.
    Type: Application
    Filed: July 6, 2022
    Publication date: October 27, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Jun OGI, Yoshiaki TASHIRO, Takahiro TOYOSHIMA, Yorito SAKANO, Yusuke OIKE, Hongbo ZHU, Keiichi NAKAZAWA, Yukari TAKEYA, Atsushi OKUYAMA, Yasufumi MIYOSHI, Ryosuke MATSUMOTO, Atsushi HORIUCHI
  • Publication number: 20220271070
    Abstract: There is provided a solid-state imaging device including: a first semiconductor layer including a photoelectric converter and an electric charge accumulation section for each pixel, the electric charge accumulation section in which a signal electric charge generated in the photoelectric converter is accumulated; a pixel separation section that is provided in the first semiconductor layer, and partitions a plurality of the pixels from each other; a second semiconductor layer that is provided with a pixel transistor and is stacked on the first semiconductor layer, the pixel transistor that reads the signal electric charge of the electric charge accumulation section; and a first shared coupling section that is provided between the second semiconductor layer and the first semiconductor layer, and is provided to straddle the pixel separation section and is electrically coupled to a plurality of the electric charge accumulation sections.
    Type: Application
    Filed: June 26, 2020
    Publication date: August 25, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Keiichi NAKAZAWA, Koichiro ZAITSU, Nobutoshi FUJII, Yohei HIURA, Shigetaka MORI, Shintaro OKAMOTO, Keiji OHSHIMA, Shuji MANDA, Junpei YAMAMOTO, Yui YUGA, Shinichi MIYAKE, Tomoki KAMBE, Ryo OGATA, Tatsuki MIYAJI, Shinji NAKAGAWA, Hirofumi YAMASHITA, Yasushi HAMAMOTO, Naohiko KIMIZUKA
  • Patent number: 11424281
    Abstract: To realize miniaturization of a pixel, reduction in noise, and high quantum efficiency, and to improve short-wavelength sensitivity while suppressing inter-pixel interference and variations for each pixel. According to the present disclosure, there is provided an imaging device including: a first semiconductor layer formed in a semiconductor substrate; a second semiconductor layer of a conductivity type opposite to a conductivity type of the first semiconductor layer formed on the first semiconductor layer; a pixel separation unit which defines a pixel region including the first semiconductor layer and the second semiconductor layer; a first electrode which is connected to the first semiconductor layer from one surface side of the semiconductor substrate; and a second electrode which is connected to the second semiconductor layer from a light irradiation surface side that is the other surface of the semiconductor substrate, and is formed to correspond to a position of the pixel separation unit.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: August 23, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Jun Ogi, Yoshiaki Tashiro, Takahiro Toyoshima, Yorito Sakano, Yusuke Oike, Hongbo Zhu, Keiichi Nakazawa, Yukari Takeya, Atsushi Okuyama, Yasufumi Miyoshi, Ryosuke Matsumoto, Atsushi Horiuchi
  • Publication number: 20220165767
    Abstract: An imaging device according to an embodiment of the present disclosure includes: a first substrate including, in a first semiconductor substrate, a sensor pixel that performs photoelectric conversion; a second substrate including, in a second semiconductor substrate, a readout circuit that outputs a pixel signal based on electric charges outputted from the sensor pixel, the second substrate being stacked on the first substrate; a first insulating layer provided between the first semiconductor substrate and the second semiconductor substrate; and a second insulating layer provided between the first semiconductor substrate and the second semiconductor substrate, and having lower film density than the first insulating layer.
    Type: Application
    Filed: February 13, 2020
    Publication date: May 26, 2022
    Inventors: NOBUTOSHI FUJII, KATSUNORI HIRAMATSU, KEIICHI NAKAZAWA
  • Patent number: 11127771
    Abstract: Solid-state imaging devices, methods of producing a solid-state imaging device, and electronic apparatuses are provided. More particularly, a solid-state image device includes a silicon substrate, and at least a first photodiode formed in the silicon substrate. The device also includes an epitaxial layer with a first surface adjacent a surface of the silicon substrate, and a transfer transistor with a gate electrode that extends from the at least a first photodiode to a second surface of the epitaxial layer opposite the first surface. In further embodiments, a solid-state imaging device with a plurality of pixels formed in a second semiconductor substrate wherein the pixels are symmetrical with respect to a center point is provided. A floating diffusion is formed in an epitaxial layer, and a plurality of transfer gate electrodes that are each electrically connected to the floating diffusion by one of the transfer gate electrodes is provided.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: September 21, 2021
    Assignee: SONY CORPORATION
    Inventors: Yusuke Tanaka, Toshifumi Wakano, Keiji Tatani, Takashi Nagano, Hayato Iwamoto, Keiichi Nakazawa, Tomoyuki Hirano, Shinpei Yamaguchi, Shunsuke Maruyama
  • Patent number: 11094725
    Abstract: Solid-state imaging devices, methods of producing a solid-state imaging device, and electronic apparatuses are provided. More particularly, a solid-state image device includes a silicon substrate, and at least a first photodiode formed in the silicon substrate. The device also includes an epitaxial layer with a first surface adjacent a surface of the silicon substrate, and a transfer transistor with a gate electrode that extends from the at least a first photodiode to a second surface of the epitaxial layer opposite the first surface. In further embodiments, a solid-state imaging device with a plurality of pixels formed in a second semiconductor substrate wherein the pixels are symmetrical with respect to a center point is provided. A floating diffusion is formed in an epitaxial layer, and a plurality of transfer gate electrodes that are each electrically connected to the floating diffusion by one of the transfer gate electrodes is provided.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: August 17, 2021
    Assignee: SONY CORPORATION
    Inventors: Yusuke Tanaka, Toshifumi Wakano, Keiji Tatani, Takashi Nagano, Hayato Iwamoto, Keiichi Nakazawa, Tomoyuki Hirano, Shinpei Yamaguchi, Shunsuke Maruyama