Patents by Inventor Keiichi Sano

Keiichi Sano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220193751
    Abstract: A method of manufacturing a plunger pump includes a temperature difference generation process of generating a difference in temperature with respect to a normal temperature state for either one of an outer cylinder or an inner cylinder, a cylinder insertion process of inserting the inner cylinder inside the outer cylinder in a state in which the inner cylinder has a smaller outer diameter than an inner diameter of the outer cylinder as a result of the temperature difference generated by the temperature difference generation process, an elimination process of eliminating the generated temperature difference, and a plunger placement process of placing a circular tube-shaped plunger in a pressure chamber of the inner cylinder so as to enable of reciprocating motion by the plunger.
    Type: Application
    Filed: March 16, 2020
    Publication date: June 23, 2022
    Inventor: Keiichi Sano
  • Publication number: 20210157977
    Abstract: A display system includes a processing device. The processing device is operable for, upon receiving a sentence inputted by a user, extracting a keyword from the sentence, and generating a chart related to the keyword from prescribed data and displaying the chart on a first screen.
    Type: Application
    Filed: February 4, 2021
    Publication date: May 27, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideki YASUI, Keiichi SANO, Masaya MOTOKUBOTA, Koichi YAMAGATA
  • Publication number: 20190392032
    Abstract: According to one embodiment, a display system includes a processing device. The processing device is operable for, upon receiving a sentence inputted by a user, extracting a keyword from the sentence, and generating a chart related to the keyword from prescribed data and displaying the chart on a first screen.
    Type: Application
    Filed: March 26, 2019
    Publication date: December 26, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideki YASUI, Keiichi SANO, Masaya MOTOKUBOTA, Koichi YAMAGATA
  • Patent number: 10311789
    Abstract: A pixel circuit includes a selection transistor, a driving transistor, an emissive element, a first capacitor, and a reference transistor. The selection transistor is coupled to a gate line and a data line. A control electrode of the driving transistor is coupled to the selection transistor and a first electrode of the driving transistor is coupled to a power source line. The emissive element emits light according to a current drawn from the driving transistor. The first capacitor is coupled to the driving transistor and an emission signal line. A control electrode of the reference transistor is coupled to a reference signal line providing a selectable voltage with a first predetermined level and a second predetermined level. A first electrode of the reference transistor is coupled to the control electrode of the driving transistor.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: June 4, 2019
    Assignee: AOT LIMITED
    Inventors: Keiichi Sano, Ryuji Nishikawa
  • Patent number: 10262596
    Abstract: A pixel circuit includes a selection transistor, a driving transistor, an emissive element, a first capacitor, a reference transistor and a second capacitor. The selection transistor is coupled to a gate line and a data line. A control electrode of the driving transistor is coupled to the selection transistor and a first electrode of the driving transistor is coupled to a power source line. The emissive element emits light according to a current drawn from the driving transistor. The first capacitor is coupled to the driving transistor and an emission signal line. A control electrode of the reference transistor is coupled to a first voltage source. A second electrode of the reference transistor is coupled to the control electrode of the driving transistor. The second capacitor is coupled to a second voltage source and the reference transistor.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: April 16, 2019
    Assignee: AOT LIMITED
    Inventors: Keiichi Sano, Ryuji Nishikawa
  • Publication number: 20180211594
    Abstract: A pixel circuit includes a selection transistor, a driving transistor, an emissive element, a first capacitor, and a reference transistor. The selection transistor is coupled to a gate line and a data line. A control electrode of the driving transistor is coupled to the selection transistor and a first electrode of the driving transistor is coupled to a power source line. The emissive element emits light according to a current drawn from the driving transistor. The first capacitor is coupled to the driving transistor and an emission signal line. A control electrode of the reference transistor is coupled to a reference signal line providing a selectable voltage with a first predetermined level and a second predetermined level. A first electrode of the reference transistor is coupled to the control electrode of the driving transistor.
    Type: Application
    Filed: January 17, 2018
    Publication date: July 26, 2018
    Applicant: FORDLEY Hong Kong Limited
    Inventors: Keiichi SANO, Ryuji NISHIKAWA
  • Publication number: 20180068619
    Abstract: A pixel circuit includes a selection transistor, a driving transistor, an emissive element, a first capacitor, a reference transistor and a second capacitor. The selection transistor is coupled to a gate line and a data line. A control electrode of the driving transistor is coupled to the selection transistor and a first electrode of the driving transistor is coupled to a power source line. The emissive element emits light according to a current drawn from the driving transistor. The first capacitor is coupled to the driving transistor and an emission signal line. A control electrode of the reference transistor is coupled to a first voltage source. A second electrode of the reference transistor is coupled to the control electrode of the driving transistor. The second capacitor is coupled to a second voltage source and the reference transistor.
    Type: Application
    Filed: September 7, 2017
    Publication date: March 8, 2018
    Applicant: FORDLEY Hong Kong Limited
    Inventors: Keiichi SANO, Ryuji NISHIKAWA
  • Patent number: 7952546
    Abstract: A sample/hold circuit is appropriate for a pixel unit including a liquid crystal capacitor and includes a sampling transistor, a sampling capacitor, a first switching transistor, and a second switching transistor. The sampling transistor is coupled to the liquid crystal capacitor for sampling a voltage stored in the liquid crystal capacitor. The sampling capacitor stores the sampling result. The first switching transistor includes a gate and a source respectively coupled to two terminals of the sampling capacitor. The second switching transistor includes a gate and a drain respectively coupled to the terminals of the sampling capacitor.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: May 31, 2011
    Assignee: Chimei Innolux Corporation
    Inventor: Keiichi Sano
  • Patent number: 7742044
    Abstract: A source-follower-type analogue buffer with an active load, a new compensating operation and a display with the source-follower-type analogue buffers are developed to reduce an error voltage which is the difference between an input voltage and an output voltage of the analogue buffer. The source-follower type analogue buffer can also minimize the variation from both the charging time and the device characteristics and maximize the range of the input voltage.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: June 22, 2010
    Assignee: TPO Displays Corp.
    Inventors: Cheng-Ho Yu, Fu-Yuan Hsueh, Wei-Cheng Lin, Keiichi Sano, Ya-Hsiang Tai
  • Patent number: 7714828
    Abstract: A display capable of reducing the increase in the current consumption is disclosed. The display comprises a shift register circuit having a plurality of first circuit portions connected thereto. Each of the first circuit portions includes a first conductive type first transistor connected to a first voltage supply source, a first conductive type second transistor connected to a second voltage supply source, a first conductive type third transistor connected between the gate of the first transistor and the second potential, a first conductive type fourth transistor connected to the gate of the first transistor and turned on in response to a first signal, and a first conductive type fifth transistor connected between the fourth transistor and the first potential and turned off in response to a second signal when the first signal is for turning on the fourth transistor.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: May 11, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Keiichi Sano
  • Patent number: 7667177
    Abstract: A reading circuit including a detection module, a first transistor, and a compensation module is disclosed. The detection module detects a light. The first transistor transforms the detection result for generating a current signal. The compensation module compensates a threshold voltage of the first transistor.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: February 23, 2010
    Assignee: TPO Displays Corp.
    Inventor: Keiichi Sano
  • Publication number: 20090278121
    Abstract: A system for displaying images includes a thin film transistor array substrate including a substrate with thin film transistors array and at least one light-sensing element containing an amorphous silicon layer formed on the substrate, wherein the light-sensing element has a current flow direction perpendicular to the substrate.
    Type: Application
    Filed: April 21, 2009
    Publication date: November 12, 2009
    Applicant: TPO Displays Corp.
    Inventors: Ramesh Kakkad, Keiichi Sano, Fu-Yuan Hsueh, Chih-Chung Liu, Sheng-Wen Chang
  • Patent number: 7586468
    Abstract: A video signal line receives a voltage video signal. The supplied voltage video signal is provided to a voltage-current conversion circuit in a corresponding column. The voltage-current conversion circuit converts the voltage video signal into a current signal, and supplies the current signal to a corresponding pixel circuit. Each voltage-current conversion circuit includes an output transistor for supplying current in accordance with the voltage video signal, and a compensation circuit for compensating for variations in threshold of the output transistor.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: September 8, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Keiichi Sano
  • Publication number: 20090128473
    Abstract: Active matrix display devices capable of improving aperture ratio of pixels and of smoothing intermediate colors are presented. An active matrix display device has static random access memory (SRAM) devices and digital to analog converters (DAC), which are both allocated to each of sub-pixels divided by a pixel. The SRAM stores an input digital data with over two bits, which can be used as gradient information for gray scale display of the sub-pixels. The input digital data is converted into analog data for display by the DAC. Gray scale display of the sub-pixels can be performed based on gray scales determined by the analog data for display. The pixel can be used to display multiple gray scales according to combinations of areas and gray scales of the sub-pixels.
    Type: Application
    Filed: November 7, 2008
    Publication date: May 21, 2009
    Applicant: TPO Displays Corp.
    Inventors: Keitaro YAMASHITA, Keiichi Sano, Masahiro Yoshiga
  • Patent number: 7525467
    Abstract: A digital to analog converter is provided comprising a charge sharing circuit, a discharging circuit and a voltage boosting circuit. The charge sharing circuit sequentially receives first to (N?1)th bits of serial digital signals. The charge sharing circuit shares and stores charges between a first capacitor and a second capacitor according to a charging voltage, a ground voltage, a first clock signal and serial data signals. The discharging circuit discharges the charge sharing circuit according to a reset signal. After the voltage boosting circuit receive the (N?1)th digital signal, the charge boosting circuit whether to boost a first terminal and a second terminal of the second capacitor or not based on an Nth digital signal. After the voltage boosting circuit receives the Nth serial digital signal, the charge sharing circuit outputs an analog signal from the second terminal of the second capacitor.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: April 28, 2009
    Assignee: TPO Displays Corp.
    Inventors: Wei-Cheng Lin, Kai-Chieh Yang, Keiichi Sano, Fang-Hsing Wang, Ting-Yu Chang
  • Publication number: 20090020686
    Abstract: A reading circuit including a detection module, a first transistor, and a compensation module is disclosed. The detection module detects a light. The first transistor transforms the detection result for generating a current signal. The compensation module compensates a threshold voltage of the first transistor.
    Type: Application
    Filed: July 19, 2007
    Publication date: January 22, 2009
    Applicant: TPO DISPLAYS CORP.
    Inventor: Keiichi Sano
  • Patent number: 7474284
    Abstract: A display capable of suppressing the increase in current consumption is disclosed. The display comprises a first transistor connected to a first potential, a second transistor connected to a second potential, a third transistor for turning off the first transistor when the second transistor is in on state, a fourth transistor connected to the first potential, a fifth transistor connected to the second potential, and a sixth transistor operated to turn off when the third transistor is in on state and also operated to turn off the fourth transistor when the fifth transistor is in on state.
    Type: Grant
    Filed: May 4, 2004
    Date of Patent: January 6, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Keiichi Sano
  • Publication number: 20090002582
    Abstract: A sample/hold circuit is appropriate for a pixel unit including a liquid crystal capacitor and includes a sampling transistor, a sampling capacitor, a first switching transistor, and a second switching transistor. The sampling transistor is coupled to the liquid crystal capacitor for sampling a voltage stored in the liquid crystal capacitor. The sampling capacitor stores the sampling result. The first switching transistor includes a gate and a source respectively coupled to two terminals of the sampling capacitor. The second switching transistor includes a gate and a drain respectively coupled to the terminals of the sampling capacitor.
    Type: Application
    Filed: June 27, 2007
    Publication date: January 1, 2009
    Applicant: TPO DISPLAYS CORP.
    Inventor: Keiichi Sano
  • Patent number: 7463224
    Abstract: Each pixel in a display device includes an emissive element, a driver transistor, a control transistor, and a control capacitor. The driver transistor is provided between the emissive element and a power supply and controls supply of power from the power supply to the emissive element. The control transistor is connected between a constant voltage power supply and a gate of the driver transistor, receives a digital data signal on a gate, and controls whether or not to fix a gate voltage of the driver transistor. The control capacitor is connected between a control line and the gate of the driver transistor. The gate voltage of the driver transistor is shifted to a voltage corresponding to a control pulse signal when the control transistor is off and is non-fixed during a light emission period defined by the control pulse signal applied to the control line.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: December 9, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Keiichi Sano
  • Publication number: 20080259005
    Abstract: A display panel including a first sub-pixel, a second sub-pixel, and a processing unit is disclosed. The first sub-pixel includes a first storage capacitor for storing a first voltage. The second sub-pixel includes a second storage capacitor for storing a second voltage. The processing unit processes the first voltage and transmits the processed result to the first or the second capacitor according to a control signal group.
    Type: Application
    Filed: April 23, 2007
    Publication date: October 23, 2008
    Applicant: TPO DISPLAYS CORP.
    Inventor: Keiichi Sano