Abstract: A digital to analog converter is provided comprising a charge sharing circuit, a discharging circuit and a voltage boosting circuit. The charge sharing circuit sequentially receives first to (N-1)th bits of serial digital signals. The charge sharing circuit shares and stores charges between a first capacitor and a second capacitor according to a charging voltage, a ground voltage, a first clock signal and serial data signals. The discharging circuit discharges the charge sharing circuit according to a reset signal. After the voltage boosting circuit receive the (N-1)th digital signal, the charge boosting circuit whether to boost a first terminal and a second terminal of the second capacitor or not based on an Nth digital signal. After the voltage boosting circuit receives the Nth serial digital signal, the charge sharing circuit outputs an analog signal from the second terminal of the second capacitor.

Abstract: A signal sampled by a sampling transistor is amplified with low power consumption. A display voltage signal Vsig sampled by the sampling transistor is amplified by an amplifier circuit of this invention. A thin film transistor T1 which functions as a MOS capacitance is connected to a signal line DL to which the display voltage signal Vsig is outputted. A voltage boosting pulse VP1 is applied to a gate of the thin film transistor T1. And the thin film transistor T1 is switched from ON to OFF during change in the rising pulse. The amplifier circuit amplifies the signal through the use of difference between the gate capacitance of the thin film transistor T1 in ON state and the gate capacitance of the thin film transistor T1 in OFF state.

Abstract: Systems for displaying images. The system comprises a display panel comprising a plurality of data lines DL(x), a plurality of gate lines SL(y) perpendicular to the data lines DL(x), and a pixel array coupled to the data lines and the gate lines. The pixel array comprises a first pixel P(x+1, y) coupled to the gate line SL(y+1) and the data line DL(x+1), a second pixel P(x+1, y+1) coupled to the gate line SL(y+1) and the data line DL(x+2), a third pixel P(x, y+1) coupled to the gate line SL(y+2) and the data line DL(x+1), and a fourth pixel P(x, y+2) coupled to the gate line SL(y+2) and the data line DL(x).

Abstract: When a switching TFT is switched on, a data voltage on a data line is stored in a storage capacitor as a gate voltage of a driver TFT. In this state, a voltage on a pulse drive line is caused to fall. AMOS type capacity element having a second electrode connected to a reference voltage is connected to a gate of the driver TFT. The MOS type capacity element is in an ON state before a fall of the pulse drive line and becomes an OFF state during the fall, and a capacitance changes at the switching of ON state to the OFF state. Therefore, the slope of fall of the gate voltage changes, and the gate voltage after the fall on the pulse drive line can be corrected corresponding to the variation in the threshold values among driver TFTs.

Abstract: Systems for displaying images. The system comprises a digital-to-analog converter, in which a first conversion stage selects first and second voltages of a plurality of reference voltages according to m most significant bits of a k bit input signal; and a second conversion stage converting n least significant bits of the k bit input signal to a voltage between the first and second voltages. In the second conversion stage, according to first and second bits of the least significant bits, a first switching capacitor unit charges a first capacitor during a first period and then the second switching capacitor unit performs a first charge sharing between the first capacitor and a second capacitor, and the first switching capacitor unit charges the first capacitor again and then the second switching capacitor unit performs a second charge sharing between the first capacitor and the second capacitor.

Abstract: Driving methods and devices are provided. In a representative method, Nth and (N+K)th rows of pixels are scanned sequentially and a signal of a first polarity is provided in sequence to the Nth and (N+K)th rows of scanned pixels, during a first period of a frame period. During a second period of the frame period, (N+l)th and (N+K+1)th rows of pixels are scanned sequentially and a signal of a second polarity is provided in sequence to the (N+1)th and (N+K+1)th rows of scanned pixels, wherein N and K are both integers, N>0, K is even and K>1.

Abstract: A source-follower-type analogue buffer with an active load, a new compensating operation and a display with the source-follower-type analogue buffers are developed to reduce an error voltage which is the difference between an input voltage and an output voltage of the analogue buffer. The source-follower type analogue buffer can also minimize the variation from both the charging time and the device characteristics and maximize the range of the input voltage.

Abstract: A display device in which variations of characteristics of a TFT are eliminated and the aperture ratio is improved is provided. A display device has a thin film transistor on an insulating substrate 10. The thin film transistor includes first gate electrodes 11, a gate insulating film 12, a semiconductor film 13 which is formed on the first gate electrode 11, and a interlayer insulating film 15. The thin film transistor further includes second gate electrodes 70 which are on the interlayer insulating film 15 and at least above channels 13c, and which are connected to the first gate electrodes 11. A reflective display electrode 19 connected to the source of the thin film transistor is elongated to extend above the thin film transistor.

Abstract: Displays and driving methods capable of reducing power consumption caused by changing polarity on the data lines. In the display, a pixel array comprises a plurality of data lines, and a plurality of pixels each pixel comprising of a red sub-pixel, a green sub-pixel and a blue sub-pixel. A source output circuit provides a first series of source output signals with a first polarity through a first output pin and a second series of source output signals with a second polarity through a second output pin for an operation period. A switching array circuit comprises at least three select lines and electrically connects the first series of source output signals and the second series of source output signals to at least some of the sub-pixels of two adjacent pixels.

Abstract: A semiconductor device for individually controlling an element to be driven, such as an electroluminescence element, includes a switching TFT which operates when a selection signal is applied to its gate and which also captures a data signal, and an element-driving TFT in which its drain is connected with a drive power source, its source is connected with the element to be driven, gate receives a data signal supplied from the switching TFT, for controlling electric power supplied from the drive power source to the element to be driven. The semiconductor device further includes a storage capacitor having a first electrode connected with the switching TFT and with the gate of the element-driving TFT and a second electrode connected between the source of the element-driving TFT and the element to be driven, for holding the gate-source voltage of the element-driving TFT in accordance with the data signal, and a switching element for controlling the potential of the second electrode of the storage capacitor.

Abstract: A semiconductor device for individually controlling an element to be driven, such as an electroluminescence element, includes a switching TFT which operates when a selection signal is applied to its gate and which also captures a data signal, and an element-driving TFT in which its drain is connected with a drive power source, its source is connected with the element to be driven, gate receives a data signal supplied from the switching TFT, for controlling electric power supplied from the drive power source to the element to be driven. The semiconductor device further includes a storage capacitor having a first electrode connected with the switching TFT and with the gate of the element-driving TFT and a second electrode connected between the source of the element-driving TFT and the element to be driven, for holding the gate-source voltage of the element-driving TFT in accordance with the data signal, and a switching element for controlling the potential of the second electrode of the storage capacitor.

Abstract: A display capable of reducing the increase in the current consumption is disclosed. The display comprises a shift register circuit having a plurality of first circuit portions connected thereto. Each of the first circuit portions includes a first conductive type first transistor connected to a first voltage supply source, a first conductive type second transistor connected to a second voltage supply source, a first conductive type third transistor connected between the gate of the first transistor and the second potential, a first conductive type fourth transistor connected to the gate of the first transistor and turned on in response to a first signal, and a first conductive type fifth transistor connected between the fourth transistor and the first potential and turned off in response to a second signal when the first signal is for turning on the fourth transistor.

Abstract: The invention is directed to simplification of a structure of a drive circuit disposed on a periphery of a pixel region to reduce a frame area of a display panel and power consumption. In a pixel, a TFT (T1), a TFT (T2), and a TFT (T3) are serially connected. The TFT (T1) is connected with a drain signal line DL1, and the TFT (T3) is connected with a pixel electrode of a liquid crystal. A first terminal of each of the first capacitor and the second capacitor is applied with ground potential (0V). A second terminal of the first capacitor is connected with a connection point of the TFT (T1) and the TFT (T2). A second terminal of the second capacitor is connected with a connection point of the TFT (T2) and the TFT (T3). Gates of the TFT (T1), the TFT (T2), and the TFT (T3) are respectively applied with control pulse signals A, B, and C for controlling on and off of these TFTs.

Abstract: Each pixel in a display device includes an emissive element, a driver transistor, a control transistor, and a control capacitor. The driver transistor is provided between the emissive element and a power supply and controls supply of power from the power supply to the emissive element. The control transistor is connected between a constant voltage power supply and a gate of the driver transistor, receives a digital data signal on a gate, and controls whether or not to fix a gate voltage of the driver transistor. The control capacitor is connected between a control line and the gate of the driver transistor. The gate voltage of the driver transistor is shifted to a voltage corresponding to a control pulse signal when the control transistor is off and is non-fixed during a light emission period defined by the control pulse signal applied to the control line.

Abstract: A video signal line receives a voltage video signal. The supplied voltage video signal is provided to a voltage-current conversion circuit in a corresponding column. The voltage-current conversion circuit converts the voltage video signal into a current signal, and supplies the current signal to a corresponding pixel circuit. Each voltage-current conversion circuit includes an output transistor for supplying current in accordance with the voltage video signal, and a compensation circuit for compensating for variations in threshold of the output transistor.

Abstract: When a switching TFT is switched on, a data voltage on a data line is stored in a storage capacitor as a gate voltage of a driver TFT. In this state, a voltage on a pulse drive line is caused to fall. AMOS type capacity element having a second electrode connected to a reference voltage is connected to a gate of the driver TFT. The MOS type capacity element is in an ON state before a fall of the pulse drive line and becomes an OFF state during the fall, and a capacitance changes at the switching of ON state to the OFF state. Therefore, the slope of fall of the gate voltage changes, and the gate voltage after the fall on the pulse drive line can be corrected corresponding to the variation in the threshold values among driver TFTs.

Abstract: A signal sampled by a sampling transistor is amplified with low power consumption. A display voltage signal Vsig sampled by the sampling transistor is amplified by an amplifier circuit of this invention. A thin film transistor T1 which functions as a MOS capacitance is connected to a signal line DL to which the display voltage signal Vsig is outputted. A voltage boosting pulse VP1 is applied to a gate of the thin film transistor T1. And the thin film transistor T1 is switched from ON to OFF during change in the rising pulse. The amplifier circuit amplifies the signal through the use of difference between the gate capacitance of the thin film transistor T1 in ON state and the gate capacitance of the thin film transistor T1 in OFF state.

Abstract: A display capable of suppressing the increase in current consumption is disclosed. The display comprises a first transistor connected to a first potential, a second transistor connected to a second potential, a third transistor for turning off the first transistor when the second transistor is in on state, a fourth transistor connected to the first potential, a fifth transistor connected to the second potential, and a sixth transistor operated to turn off when the third transistor is in on state and also operated to turn off the fourth transistor when the fifth transistor is in on state.

Abstract: A display device in which variations of characteristics of a TFT are eliminated and the aperture ratio is improved is provided. A display device has a thin film transistor on an insulating substrate 10. The thin film transistor includes first gate electrodes 11, a gate insulating film 12, a semiconductor film 13 which is formed on the first gate electrode 11, and a interlayer insulating film 15. The thin film transistor further includes second gate electrodes 70 which are on the interlayer insulating film 15 and at least above channels 13c, and which are connected to the first gate electrodes 11. A reflective display electrode 19 connected to the source of the thin film transistor is elongated to extend above the thin film transistor.

Abstract: A pair of storage capacitor electrodes are extended along a data line to provide storage capacitance along the data line. One of the storage capacitor electrodes is a metal electrode which partially overlaps the data line. Light can thereby be shielded in a region between the data line and a pixel electrode while forming a storage capacitor. The other storage capacitor electrode is positioned so as to avoid overlapping the data line, thereby suppressing coupling between the data line and the other storage capacitor electrode.