Patents by Inventor Keiichi Yamaguchi

Keiichi Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120154034
    Abstract: According to an embodiment, a Doherty amplifier system has a first Doherty amplifier and a second Doherty amplifier. The first Doherty amplifier operates in a SISO communication mode and in a MIMO communication mode. The first Doherty amplifier comprises a first carrier amplifier and a first peak amplifier. The second Doherty amplifier operates in the MIMO communication mode but not operates in the SISO communication mode. The second Doherty amplifier comprises a second carrier amplifier and a second peak amplifier. A distance between the first carrier amplifier and the second carrier amplifier is less than any of a distance between any of the first carrier amplifier and the second peak amplifier and any of the first peak amplifier and the second peak amplifier. In the SISO communication mode, heat generated by the first Doherty amplifier is conducted to the second Doherty amplifier to warm up the second Doherty amplifier.
    Type: Application
    Filed: February 22, 2012
    Publication date: June 21, 2012
    Inventors: Takayuki Kato, Atsushi Yamaoka, Keiichi Yamaguchi
  • Patent number: 8204454
    Abstract: This distortion compensator apparatus is a distortion compensator apparatus compensating nonlinearity of an amplifier and includes: a memory storing a compensation parameter used for correcting an input signal of the amplifier; a compensator correcting the input signal of the amplifier based on the compensation parameter; and an update controller updating the compensation parameter according to an operation state of the amplifier.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: June 19, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yamaoka, Keiichi Yamaguchi
  • Patent number: 7981807
    Abstract: Cost is reduced and reliability is improved with a CSP type semiconductor device. A glass substrate which works as a supporting plate is bonded through an adhesive to a first surface of a semiconductor wafer on which first wirings are formed. Thickness of the semiconductor wafer is reduced by back-grinding the semiconductor wafer on a second surface of the semiconductor wafer which is opposite to the first surface of the semiconductor wafer. The semiconductor wafer is wet-etched to remove bumps and dips on the second surface of the semiconductor wafer caused during the back-grinding. Then the second surface of the semiconductor wafer is etched to form a tapered groove. The semiconductor wafer is wet-etched to reduce bumps and dips caused by the etching and round a corner of the groove. The wet-etching improves coverage of insulation film, wiring and protection film and enhances yield and reliability of the semiconductor device.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: July 19, 2011
    Assignee: SANYO Electric Co., Ltd.
    Inventors: Akira Suzuki, Takashi Noma, Hiroyuki Shinogi, Yukihiro Takao, Shinzo Ishibe, Shigeki Otsuka, Keiichi Yamaguchi
  • Patent number: 7974654
    Abstract: A communication apparatus, includes unit extracting a reception key feature of a temporal change in received power in each frequency band contained in a received signal, unit storing, in correspondence with one another, a system name of a system which uses the frequency band, event information indicating that a communication apparatus belonging to the system starts or stops transmission, and a transmission key feature of a temporal waveform change shape of a transmission signal from a communication apparatus belonging to the system, a transmission key feature corresponding to the event information, unit determining whether there is any transmission key feature matching the reception key feature, by comparing the reception key feature with the transmission key feature, and unit selecting, when the determination unit determines that there is a matched transmission key feature, the event information and the system name which correspond to the transmission key feature from the storage unit.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: July 5, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tazuko Tomioka, Keiichi Yamaguchi, Tomoya Horiguchi
  • Patent number: 7974494
    Abstract: Image control involves receiving source images defined with respect to respective source coordinate systems from source image generators also respectively associated with source IDs. The source images are composed to generate a composite image defined with respect to a composed coordinate system, and the composed image is sent to a viewer which displays the composed image and outputs an HID signal which indicates information defined with respect to the composed coordinate system. A layout manager stores source IDs respectively associated with layout information including position and size of at least one of the source images. An image composer composes the source images according to the layout information. An analyzer analyzes the HID signal for editing layout information stored in the layout manager, and determines a source ID a source image according to the layout information.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: July 5, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuya Kawamura, Shinya Murai, Kotaro Ise, Masataka Goto, Keiichi Yamaguchi
  • Patent number: 7959870
    Abstract: An unloading device includes: a separator connected to a suction hose connected to the reactor and to another suction hose connected to a vacuum car, the separator separating a catalyst sucked from the reactor by the vacuum car from air; a flexible container bag for storing the catalyst dropped from the separator; and a dumping hose provided between the separator and the flexible container bag for transferring the catalyst dropped from the separator to the flexible container bag. The separator includes a blower unit for blowing a gas to the catalyst unloaded in the separator body toward a lower cone and a cover that openably closes a catalyst outlet.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: June 14, 2011
    Assignee: Softard Industries Co., Ltd.
    Inventors: Tomokazu Yanokuchi, Keiichi Yamaguchi, Masayuki Kidokoro, Katsuhiko Kawakami
  • Patent number: 7919875
    Abstract: A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window to expose first wirings is formed only in a region of a semiconductor substrate where the first wirings exist. As a result, area of the semiconductor substrate bonded to a supporting body through an insulation film and a resin is increased to prevent cracks in the supporting body and separation of the semiconductor substrate from the supporting body. A slit is formed along a dicing line after forming the window, the slit is covered with a protection film and then the semiconductor substrate is diced into individual semiconductor dice. Thus, separation on a cut surface or at an edge of the semiconductor dice, which otherwise would be caused by contact of the blade in the dicing can be prevented.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: April 5, 2011
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductor Co., Ltd.
    Inventors: Takashi Noma, Katsuhiko Kitagawa, Hisao Otsuka, Akira Suzuki, Yoshinori Seki, Yukihiro Takao, Keiichi Yamaguchi, Motoaki Wakui, Masanori Iida
  • Patent number: 7778354
    Abstract: A communicating apparatus includes: a local signal generator, an orthogonal modulator, an orthogonal demodulator, and two orthogonal error compensators. The local signal generator generates a first local signal and a second local signal. The orthogonal modulator modulates an input signal into a modulation signal by using the first local signal. The orthogonal demodulator demodulates the modulation signal into a demodulation signal by using the second local signal. Each of the two orthogonal error compensators corrects orthogonal modulation error generated in the orthogonal modulator and an orthogonal demodulation error generated in the orthogonal demodulator respectively. Set values to be set to the orthogonal error compensators are calculated based on (1) a phase difference between the first local signal and the second local signal, (2) the input signal and (3) the demodulation signal.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: August 17, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiichi Yamaguchi, Atsushi Yamaoka
  • Publication number: 20100159856
    Abstract: A distortion compensator for reducing a level of a distortion component included in an output analog signal of an amplifier, includes: an A/D converter to convert the output analog signal of the amplifier into a digital output signal; a comparator to generate a distortion characteristic of the amplifier based on a digital input signal and the digital output signal; a rate controller to control a sampling rate of the A/D converter based on the digital input signal and the digital output signal; a predistorter to multiply the digital input signal and a compensation value for compensating the amplifier, the compensation value being calculated based on the digital input signal and the distortion characteristic of the amplifier; and a D/A converter to convert multiplication result of the predistorter into an analog input signal to input the analog input signal to the amplifier.
    Type: Application
    Filed: September 15, 2009
    Publication date: June 24, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takayuki Kato, Atsushi Yamaoka, Keiichi Yamaguchi
  • Publication number: 20090222593
    Abstract: There is provided with a server device which outputs a result of computation processing to an output device, including: a communication unit configured to receive a connection request from an input device; an output device manager configured to store an identifier of the output device; and an connection controller configured to acquire output capability information of the output device, configured to acquire input capability information of the input device, configured to generate secret information which can be input to the input device and can be output by the output device, on the basis of the input capability information and the output capability information, configured to transmit the secret information to the output device, and configured to generate a result of computation processing based on input information received from the input device for transmitting to the output device in a case of receiving the secret information from the input device.
    Type: Application
    Filed: March 28, 2006
    Publication date: September 3, 2009
    Inventors: Shinya Murai, Takuya Kawamura, Kotaro Ise, Keiichi Yamaguchi, Masataka Goto
  • Publication number: 20090214403
    Abstract: An unloading device includes: a separator connected to a suction hose connected to the reactor and to another suction hose connected to a vacuum car, the separator separating a catalyst sucked from the reactor by the vacuum car from air; a flexible container bag for storing the catalyst dropped from the separator; and a dumping hose provided between the separator and the flexible container bag for transferring the catalyst dropped from the separator to the flexible container bag. The separator includes a blower unit for blowing a gas to the catalyst unloaded in the separator body toward a lower cone and a cover that openably closes a catalyst outlet.
    Type: Application
    Filed: February 24, 2009
    Publication date: August 27, 2009
    Applicant: SOFTARD INDUSTRIES CO., LTD.
    Inventors: Tomokazu Yanokuchi, Keiichi Yamaguchi, Masayuki Kidokoro, Katsuhiko Kawakami
  • Publication number: 20090195309
    Abstract: This distortion compensator apparatus is a distortion compensator apparatus compensating nonlinearity of an amplifier and includes: a memory storing a compensation parameter used for correcting an input signal of the amplifier; a compensator correcting the input signal of the amplifier based on the compensation parameter; and an update controller updating the compensation parameter according to an operation state of the amplifier.
    Type: Application
    Filed: May 29, 2007
    Publication date: August 6, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yamaoka, Keiichi Yamaguchi
  • Patent number: 7557017
    Abstract: The invention is directed to improvement of reliability of a process of separating a layer to be patterned such as a wiring layer in a semiconductor device manufacturing method. A wiring layer is formed on a back surface of a semiconductor substrate. A third resist layer (positive resist layer) is formed on the wiring layer, having an opening in a predetermined region along a dicing line at a bottom of the opening, and the wiring layer is etched using the third resist layer as a mask. After the third resist layer is removed, a fourth resist layer (negative resist layer) is formed on the wiring layer so as to leave the wiring layer in a region of a predetermined pattern, and the wiring layer is etched using the fourth resist layer as a mask. The wiring layer is thus patterned so as to form the predetermined pattern and be separated at the predetermined region along the dicing line at the bottom of the opening without fail.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: July 7, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hiroshi Yamada, Keiichi Yamaguchi
  • Patent number: 7526259
    Abstract: A radio frequency circuit includes a radio frequency signal source which produces a radio frequency signal, a power amplifier which power amplifies the radio frequency signal from the radio frequency signal source, and a control unit which controls an output power of the power amplifier. Particularly, the control unit is configured to hold control data defining a relationship among an output power, a gain, and an operation bias point of the power amplifier and adjust the operation bias point of the power amplifier based on the control data such that the output power of the power amplifier is set into a level designated by an external power designating instruction.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: April 28, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keiichi Yamaguchi
  • Patent number: 7489910
    Abstract: There is provided with an amplifier comprising: first and second power amplifiers; a first path configured to output first and second input signals to the first and second power amplifiers; a second path configured to divide a first input signal, output one of divided signals to the first power amplifier and output the other divided signal to the second power amplifier; a first path changeover unit configured to change over the first and second paths; a third path configured to output first and second power amplified signals from the first and second power amplifiers; a fourth path configured to combines a first power amplified signal through an impedance conversion unit from the first power amplifier and a second power amplified signal from the second power amplifier at a combining point and output a combined signal; and a second path changeover unit configured to changeover the third and fourth paths.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: February 10, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Kato, Hiroshi Yoshida, Ichiro Seto, Keiichi Yamaguchi
  • Publication number: 20080171421
    Abstract: Cost is reduced and reliability is improved with a CSP type semiconductor device. A glass substrate which works as a supporting plate is bonded through an adhesive to a first surface of a semiconductor wafer on which first wirings are formed. Thickness of the semiconductor wafer is reduced by back-grinding the semiconductor wafer on a second surface of the semiconductor wafer which is opposite to the first surface of the semiconductor wafer. The semiconductor wafer is wet-etched to remove bumps and dips on the second surface of the semiconductor wafer caused during the back-grinding. Then the second surface of the semiconductor wafer is etched to form a tapered groove. The semiconductor wafer is wet-etched to reduce bumps and dips caused by the etching and round a corner of the groove. The wet-etching improves coverage of insulation film, wiring and protection film and enhances yield and reliability of the semiconductor device.
    Type: Application
    Filed: March 19, 2008
    Publication date: July 17, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Akira SUZUKI, Takashi Noma, Hiroyuki Shinogi, Yukihiro Takao, Shinzo Ishibe, Shigeki Otsuka, Keiichi Yamaguchi
  • Publication number: 20080161035
    Abstract: A communication apparatus, includes unit extracting a reception key feature of a temporal change in received power in each frequency band contained in a received signal, unit storing, in correspondence with one another, a system name of a system which uses the frequency band, event information indicating that a communication apparatus belonging to the system starts or stops transmission, and a transmission key feature of a temporal waveform change shape of a transmission signal from a communication apparatus belonging to the system, a transmission key feature corresponding to the event information, unit determining whether there is any transmission key feature matching the reception key feature, by comparing the reception key feature with the transmission key feature, and unit selecting, when the determination unit determines that there is a matched transmission key feature, the event information and the system name which correspond to the transmission key feature from the storage unit.
    Type: Application
    Filed: August 1, 2007
    Publication date: July 3, 2008
    Inventors: Tazuko Tomioka, Keiichi Yamaguchi, Tomoya Horiguchi
  • Publication number: 20080124915
    Abstract: An insulation film having an open part in which a silicon part is exposed at a bottom surface is formed on a silicon substrate for forming a semiconductor device. Titanium is deposited to form a titanium film on the bottom surface and side wall surfaces of the contact hole. The silicon substrate and the titanium film are reacted with each other by a first annealing process to form a titanium silicide film on the bottom surface. After the titanium film that remains on the side wall surfaces of the contact hole is removed, a hydrogen annealing process is performed. This hydrogen annealing reduces the density of the interface level in the interface between the silicon substrate, the gate insulation film on the substrate surface, or the like, and improves the characteristics of the semiconductor device. After the hydrogen annealing, tungsten is deposited in the remaining space of the contact hole to form a tungsten plug.
    Type: Application
    Filed: June 13, 2007
    Publication date: May 29, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventor: Keiichi Yamaguchi
  • Patent number: 7371693
    Abstract: Cost is reduced and reliability is improved with a CSP type semiconductor device. A glass substrate which works as a supporting plate is bonded through an adhesive to a first surface of a semiconductor wafer on which first wirings are formed. Thickness of the semiconductor wafer is reduced by back-grinding the semiconductor wafer on a second surface of the semiconductor wafer which is opposite to the first surface of the semiconductor wafer. The semiconductor wafer is wet-etched to remove bumps and dips on the second surface of the semiconductor wafer caused during the back-grinding. Then the second surface of the semiconductor wafer is etched to form a tapered groove. The semiconductor wafer is wet-etched to reduce bumps and dips caused by the etching and round a corner of the groove. The wet-etching improves coverage of insulation film, wiring and protection film and enhances yield and reliability of the semiconductor device.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: May 13, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Akira Suzuki, Takashi Noma, Hiroyuki Shinogi, Yukihiro Takao, Shinzo Ishibe, Shigeki Otsuka, Keiichi Yamaguchi
  • Publication number: 20080093708
    Abstract: A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window to expose first wirings is formed only in a region of a semiconductor substrate where the first wirings exist. As a result, area of the semiconductor substrate bonded to a supporting body through an insulation film and a resin is increased to prevent cracks in the supporting body and separation of the semiconductor substrate from the supporting body. A slit is formed along a dicing line after forming the window, the slit is covered with a protection film and then the semiconductor substrate is diced into individual semiconductor dice. Thus, separation on a cut surface or at an edge of the semiconductor dice, which otherwise would be caused by contact of the blade in the dicing can be prevented.
    Type: Application
    Filed: December 13, 2007
    Publication date: April 24, 2008
    Applicants: SANYO Electric Co., Ltd., Kanto SANYO Semiconductor Co., Ltd.
    Inventors: Takashi Noma, Katsuhiko Kitagawa, Hisao Otsuka, Akira Suzuki, Yoshinori Seki, Yukihiro Takao, Keiichi Yamaguchi, Motoaki Wakui, Masanori Iida