Patents by Inventor Keiichiro Kashihara
Keiichiro Kashihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180069044Abstract: Provided is a semiconductor device which allows an alignment mark used for the manufacturing of a solid-state image sensor (semiconductor device) having a back-side-illumination structure to be formed in a smaller number of steps. The semiconductor device includes a semiconductor layer having a first main surface and a second main surface opposing the first main surface, a plurality of photodiodes which are formed in the semiconductor layer and in each of which photoelectric conversion is performed, a light receiving lens disposed over the second main surface of the semiconductor layer to supply light to each of the photodiodes, and a mark for alignment formed inside the semiconductor layer. The mark for alignment is formed so as to extend from the first main surface toward the second main surface and have a protruding portion protruding from the second main surface in a direction toward where the light receiving lens is disposed.Type: ApplicationFiled: October 30, 2017Publication date: March 8, 2018Inventor: Keiichiro KASHIHARA
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Patent number: 9837459Abstract: Provided is a semiconductor device which allows an alignment mark used for the manufacturing of a solid-state image sensor (semiconductor device) having a back-side-illumination structure to be formed in a smaller number of steps. The semiconductor device includes a semiconductor layer having a first main surface and a second main surface opposing the first main surface, a plurality of photodiodes which are formed in the semiconductor layer and in each of which photoelectric conversion is performed, a light receiving lens disposed over the second main surface of the semiconductor layer to supply light to each of the photodiodes, and a mark for alignment formed inside the semiconductor layer. The mark for alignment is formed so as to extend from the first main surface toward the second main surface and have a protruding portion protruding from the second main surface in a direction toward where the light receiving lens is disposed.Type: GrantFiled: August 4, 2016Date of Patent: December 5, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Keiichiro Kashihara
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Publication number: 20160343760Abstract: Provided is a semiconductor device which allows an alignment mark used for the manufacturing of a solid-state image sensor (semiconductor device) having a back-side-illumination structure to be formed in a smaller number of steps. The semiconductor device includes a semiconductor layer having a first main surface and a second main surface opposing the first main surface, a plurality of photodiodes which are formed in the semiconductor layer and in each of which photoelectric conversion is performed, a light receiving lens disposed over the second main surface of the semiconductor layer to supply light to each of the photodiodes, and a mark for alignment formed inside the semiconductor layer. The mark for alignment is formed so as to extend from the first main surface toward the second main surface and have a protruding portion protruding from the second main surface in a direction toward where the light receiving lens is disposed.Type: ApplicationFiled: August 4, 2016Publication date: November 24, 2016Inventor: Keiichiro KASHIHARA
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Patent number: 9450010Abstract: Provided are a semiconductor device in which a solid-state image sensing element having a backside-illuminated structure and capacitor elements storing therein some of the charges supplied from light receiving elements has further improved reliability and a manufacturing method thereof. In the solid-state image sensing element of the semiconductor device, first and second substrates are joined together at a junction surface. The first substrate is formed with photodiodes. The second substrate is formed with the capacitor elements. The photodiodes and the capacitor elements are placed to be opposed to each other. In the first substrate, first coupling portions for coupling to the second substrate are placed. In the second substrate, second coupling portions for coupling to the first substrate are placed. A first gap portion between the first coupling portions and a second gap portion between the second coupling portions are placed to overlap a first light blocking film.Type: GrantFiled: February 5, 2016Date of Patent: September 20, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Keiichiro Kashihara
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Patent number: 9437639Abstract: Provided is a semiconductor device which allows an alignment mark used for the manufacturing of a solid-state image sensor (semiconductor device) having a back-side-illumination structure to be formed in a smaller number of steps. The semiconductor device includes a semiconductor layer having a first main surface and a second main surface opposing the first main surface, a plurality of photodiodes which are formed in the semiconductor layer and in each of which photoelectric conversion is performed, a light receiving lens disposed over the second main surface of the semiconductor layer to supply light to each of the photodiodes, and a mark for alignment formed inside the semiconductor layer. The mark for alignment is formed so as to extend from the first main surface toward the second main surface and have a protruding portion protruding from the second main surface in a direction toward where the light receiving lens is disposed.Type: GrantFiled: February 7, 2013Date of Patent: September 6, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Keiichiro Kashihara
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Publication number: 20160155766Abstract: Provided are a semiconductor device in which a solid-state image sensing element having a backside-illuminated structure and capacitor elements storing therein some of the charges supplied from light receiving elements has further improved reliability and a manufacturing method thereof. In the solid-state image sensing element of the semiconductor device, first and second substrates are joined together at a junction surface. The first substrate is formed with photodiodes. The second substrate is formed with the capacitor elements. The photodiodes and the capacitor elements are placed to be opposed to each other. In the first substrate, first coupling portions for coupling to the second substrate are placed. In the second substrate, second coupling portions for coupling to the first substrate are placed. A first gap portion between the first coupling portions and a second gap portion between the second coupling portions are placed to overlap a first light blocking film.Type: ApplicationFiled: February 5, 2016Publication date: June 2, 2016Inventor: Keiichiro KASHIHARA
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Patent number: 9293496Abstract: Provided are a semiconductor device in which a solid-state image sensing element having a backside-illuminated structure and capacitor elements storing therein some of the charges supplied from light receiving elements has further improved reliability and a manufacturing method thereof. In the solid-state image sensing element of the semiconductor device, first and second substrates are joined together at a junction surface. The first substrate is formed with photodiodes. The second substrate is formed with the capacitor elements. The photodiodes and the capacitor elements are placed to be opposed to each other. In the first substrate, first coupling portions for coupling to the second substrate are placed. In the second substrate, second coupling portions for coupling to the first substrate are placed. A first gap portion between the first coupling portions and a second gap portion between the second coupling portions are placed to overlap a first light blocking film.Type: GrantFiled: August 20, 2014Date of Patent: March 22, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Keiichiro Kashihara
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Publication number: 20150380360Abstract: A semiconductor device and a manufacturing method thereof are provided which can suppress corrosion by chemicals in processes, while preventing generation of thermal stress on a mark. A semiconductor device includes a semiconductor layer with front-side main surface and a back-side main surface opposed, to the front-side main surface, a plurality of light receiving elements formed in the semiconductor layer for performing photoelectric conversion, a light receiving lens disposed above the back-side main surface for supp_ying light to the light receiving element, and a mark formed inside the semiconductor layer. The mark extends from the front-side main surface to the back-side main surfaces The mark has a deeply located surface recessed toward the front-side main surface rather than the back-side main surface. The deeply located surface is formed of silicon.Type: ApplicationFiled: September 4, 2015Publication date: December 31, 2015Inventor: Keiichiro KASHIHARA
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Patent number: 9159762Abstract: A semiconductor device and a manufacturing method thereof are provided which can suppress corrosion by chemicals in processes, while preventing generation of thermal stress on a mark. A semiconductor device includes a semiconductor layer with a front-side main surface and a back-side main surface opposed to the front-side main surface, a plurality of light receiving elements formed in the semiconductor layer for performing photoelectric conversion, a light receiving lens disposed above the back-side main surface for supp_ying light to the light receiving element, and a mark formed inside the semiconductor layer. The mark extends from the front-side main surface to the back-side main surface. The mark has a deeply located surface recessed toward the front-side main surface rather than the back-side main surface. The deeply located surface is formed of silicon.Type: GrantFiled: April 27, 2015Date of Patent: October 13, 2015Assignee: Renesas Electronics CorporationInventor: Keiichiro Kashihara
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Publication number: 20150228682Abstract: A semiconductor device and a manufacturing method thereof are provided which can suppress corrosion by chemicals in processes, while preventing generation of thermal stress on a mark. A semiconductor device includes a semiconductor layer with a front-side main surface and a back-side main surface opposed to the front-side main surface, a plurality of light receiving elements formed in the semiconductor layer for performing photoelectric conversion, a light receiving lens disposed above the back-side main surface for supplying light to the light receiving element, and a mark formed inside the semiconductor layer. The mark extends from the front-side main surface to the back-side main surface. The mark has a deeply located surface recessed toward the front-side main surface rather than the back-side main surface. The deeply located surface is formed of silicon.Type: ApplicationFiled: April 27, 2015Publication date: August 13, 2015Inventor: Keiichiro KASHIHARA
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Patent number: 9048355Abstract: A semiconductor device and a manufacturing method thereof are provided which can suppress corrosion by chemicals in processes, while preventing generation of thermal stress on a mark. A semiconductor device includes a semiconductor layer with a front-side main surface and a back-side main surface opposed to the front-side main surface, a plurality of light receiving elements formed in the semiconductor layer for performing photoelectric conversion, a light receiving lens disposed above the back-side main surface for supplying light to the light receiving element, and a mark formed inside the semiconductor layer. The mark extends from the front-side main surface to the back-side main surface. The mark has a deeply located surface recessed toward the front-side main surface rather than the back-side main surface. The deeply located surface is formed of silicon.Type: GrantFiled: July 25, 2013Date of Patent: June 2, 2015Assignee: Renesas Electronics CorporationInventor: Keiichiro Kashihara
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Publication number: 20150054110Abstract: Provided are a semiconductor device in which a solid-state image sensing element having a backside-illuminated structure and capacitor elements storing therein some of the charges supplied from light receiving elements has further improved reliability and a manufacturing method thereof. In the solid-state image sensing element of the semiconductor device, first and second substrates are joined together at a junction surface. The first substrate is formed with photodiodes. The second substrate is formed with the capacitor elements. The photodiodes and the capacitor elements are placed to be opposed to each other. In the first substrate, first coupling portions for coupling to the second substrate are placed. In the second substrate, second coupling portions for coupling to the first substrate are placed. A first gap portion between the first coupling portions and a second gap portion between the second coupling portions are placed to overlap a first light blocking film.Type: ApplicationFiled: August 20, 2014Publication date: February 26, 2015Inventor: Keiichiro KASHIHARA
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Publication number: 20140027873Abstract: A semiconductor device and a manufacturing method thereof are provided which can suppress corrosion by chemicals in processes, while preventing generation of thermal stress on a mark. A semiconductor device includes a semiconductor layer with a front-side main surface and a back-side main surface opposed to the front-side main surface, a plurality of light receiving elements formed in the semiconductor layer for performing photoelectric conversion, a light receiving lens disposed above the back-side main surface for supplying light to the light receiving element, and a mark formed inside the semiconductor layer. The mark extends from the front-side main surface to the back-side main surface. The mark has a deeply located surface recessed toward the front-side main surface rather than the back-side main surface. The deeply located surface is formed of silicon.Type: ApplicationFiled: July 25, 2013Publication date: January 30, 2014Applicant: Renesas Electronics CorporationInventor: Keiichiro Kashihara
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Patent number: 8343827Abstract: In a CMIS device, to improve the operating characteristics of an n-channel electric field transistor that is formed by using a strained silicon technique, without degrading the operating characteristics of a p-channel field effect transistor. After forming a source/drain (an n-type extension region and an n-type diffusion region) of an nMIS and a source/drain (a p-type extension region and a p-type diffusion region) of a pMIS, the each source/drain having a desired concentration profile and resistance, a Si:C layer having a desired amount of strain is formed in the n-type diffusion region, and thus the optimum parasitic resistance and the optimum amount of strain in the Si:C layer are obtained in the source/drain of the nMIS. Moreover, by performing a heat treatment in forming the Si:C layer in a short time equal to or shorter than 1 millisecond, a change in the concentration profile of the respective p-type impurities of the already-formed p-type extension region and p-type diffusion region is suppressed.Type: GrantFiled: July 14, 2011Date of Patent: January 1, 2013Assignee: Renesas Electronics CorporationInventors: Tadashi Yamaguchi, Keiichiro Kashihara, Yoji Kawasaki
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Patent number: 8338247Abstract: To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.Type: GrantFiled: March 9, 2010Date of Patent: December 25, 2012Assignee: Renesas Electronics CorporationInventors: Tadashi Yamaguchi, Toshiaki Tsutsumi, Satoshi Ogino, Kazumasa Yonekura, Kenji Kawai, Yoshihiro Miyagawa, Tomonori Okudaira, Keiichiro Kashihara, Kotaro Kihara
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Patent number: 8148248Abstract: There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.Type: GrantFiled: March 22, 2011Date of Patent: April 3, 2012Assignee: Renesas Electronics CorporationInventors: Toshiaki Tsutsumi, Tomonori Okudaira, Keiichiro Kashihara, Tadashi Yamaguchi
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Publication number: 20120049201Abstract: In a CMIS device, to improve the operating characteristics of an n-channel electric field transistor that is formed by using a strained silicon technique, without degrading the operating characteristics of a p-channel field effect transistor. After forming a source/drain (an n-type extension region and an n-type diffusion region) of an nMIS and a source/drain (a p-type extension region and a p-type diffusion region) of a pMIS, the each source/drain having a desired concentration profile and resistance, a Si:C layer having a desired amount of strain is formed in the n-type diffusion region, and thus the optimum parasitic resistance and the optimum amount of strain in the Si:C layer are obtained in the source/drain of the nMIS. Moreover, by performing a heat treatment in forming the Si:C layer in a short time equal to or shorter than 1 millisecond, a change in the concentration profile of the respective p-type impurities of the already-formed p-type extension region and p-type diffusion region is suppressed.Type: ApplicationFiled: July 14, 2011Publication date: March 1, 2012Inventors: Tadashi YAMAGUCHI, Keiichiro Kashihara, Yoji Kawasaki
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Patent number: 8022445Abstract: A method of manufacturing a semiconductor device, including the steps of preparing a silicon substrate which has a main surface whose plane direction is a surface (100); forming an n channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) which has a gate electrode, a source region, a drain region and a channel whose channel length direction is parallel to a crystal orientation <100> of the silicon substrate; and forming NiSi over the gate electrode and NiSi2 over the source region and the drain region at the same steps.Type: GrantFiled: July 27, 2009Date of Patent: September 20, 2011Assignee: Renesas Electronics CorporationInventors: Tadashi Yamaguchi, Keiichiro Kashihara, Tomonori Okudaira, Toshiaki Tsutsumi
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Publication number: 20110207317Abstract: There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.Type: ApplicationFiled: March 22, 2011Publication date: August 25, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Toshiaki Tsutsumi, Tomonori Okudaira, Keiichiro Kashihara, Tadashi Yamaguchi
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Patent number: 7936016Abstract: There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.Type: GrantFiled: March 30, 2009Date of Patent: May 3, 2011Assignee: Renesas Electronics CorporationInventors: Toshiaki Tsutsumi, Tomonori Okudaira, Keiichiro Kashihara, Tadashi Yamaguchi