Patents by Inventor Keiji Fujimoto

Keiji Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240090527
    Abstract: A description is given of apparatus for making confectionery products (1), in particular chewing gum, comprising a cutting station comprising at least two cutting units (10, 20) arranged in succession along the production line and each comprising at least one respective pair of opposing rollers (11a, 11c) and (21a, 21c) provided with knives (30), (40) oriented obliquely with respect to the flow of feeding of a sheet of confectionery material, preferably a rubbery material, in such a way that the opposing rollers of each pair are mirrored one to the other, and with respect to the corresponding rollers of the other pair.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 21, 2024
    Applicant: Perfetti Van Melle S.P.A.
    Inventors: Massimo Rosa, Alessandro Franco, Massimiliano Moneta, Andrea Formicola, Evsen Suleymanoglu, Alessio Tulli, Keiji Fujimoto, Maurizio Deleo
  • Patent number: 11933796
    Abstract: Provided are a quality control method, a quality control system, a management apparatus, an analyzer, and a quality control abnormality determination method in which measurement results of both a quality control substance and a specimen are sufficiently utilized to improve the quality of quality control. The quality control method used in a management apparatus which is connected via a network to an analyzer installed in each of a plurality of facilities includes obtaining, from an analyzer in each facility via a network, first quality control information obtained by measuring an artificially generated quality control substance, and second quality control information obtained by measuring a plurality of specimens by the analyzer in each facility; and outputting information concerning quality control of an analyzer in at least one facility, based on the obtained first quality control information and second quality control information.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: March 19, 2024
    Assignee: SYSMEX CORPORATION
    Inventors: Keiji Fujimoto, Kazuhiko Matsuoka, Yasushi Hasui
  • Publication number: 20220354777
    Abstract: Disclosed is a confectionery product for instant optical tooth whitening comprising artificial and/or natural dyes and characterised by the ability to produce an immediate whitening effect after extremely short contact times with the teeth.
    Type: Application
    Filed: October 26, 2020
    Publication date: November 10, 2022
    Applicant: Perfetti Van Melle S.P.A.
    Inventors: Andrea Sarrica, Martin Walzl, Maurizio Deleo, Guglielmo Salmoiraghi, Livio Simone, Keiji Fujimoto, Gianni Baldi
  • Publication number: 20220276273
    Abstract: Provided are a quality control method, a quality control system, a management apparatus, an analyzer, and a quality control abnormality determination method in which measurement results of both a quality control substance and a specimen are sufficiently utilized to improve the quality of quality control. The quality control method used in a management apparatus which is connected via a network to an analyzer installed in each of a plurality of facilities includes obtaining, from an analyzer in each facility via a network, first quality control information obtained by measuring an artificially generated quality control substance, and second quality control information obtained by measuring a plurality of specimens by the analyzer in each facility; and outputting information concerning quality control of an analyzer in at least one facility, based on the obtained first quality control information and second quality control information.
    Type: Application
    Filed: May 20, 2022
    Publication date: September 1, 2022
    Inventors: Keiji FUJIMOTO, Kazuhiko MATSUOKA, Yasushi HASUI
  • Patent number: 11340242
    Abstract: Provided are a quality control method, a quality control system, a management apparatus, an analyzer, and a quality control abnormality determination method in which measurement results of both a quality control substance and a specimen are sufficiently utilized to improve the quality of quality control. The quality control method used in a management apparatus which is connected via a network to an analyzer installed in each of a plurality of facilities includes obtaining, from an analyzer in each facility via a network, first quality control information obtained by measuring an artificially generated quality control substance, and second quality control information obtained by measuring a plurality of specimens by the analyzer in each facility; and outputting information concerning quality control of an analyzer in at least one facility, based on the obtained first quality control information and second quality control information.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: May 24, 2022
    Assignee: SYSMEX CORPORATION
    Inventors: Keiji Fujimoto, Kazuhiko Matsuoka, Yasushi Hasui
  • Publication number: 20190346466
    Abstract: Provided are a quality control method, a quality control system, a management apparatus, an analyzer, and a quality control abnormality determination method in which measurement results of both a quality control substance and a specimen are sufficiently utilized to improve the quality of quality control. The quality control method used in a management apparatus which is connected via a network to an analyzer installed in each of a plurality of facilities includes obtaining, from an analyzer in each facility via a network, first quality control information obtained by measuring an artificially generated quality control substance, and second quality control information obtained by measuring a plurality of specimens by the analyzer in each facility; and outputting information concerning quality control of an analyzer in at least one facility, based on the obtained first quality control information and second quality control information.
    Type: Application
    Filed: July 29, 2019
    Publication date: November 14, 2019
    Inventors: Keiji FUJIMOTO, Kazuhiko Matsuoka, Yasushi Hasui
  • Patent number: 9275886
    Abstract: Provided is a position detecting device that is capable of precisely detecting the coordinates of the center of a disc-shaped substrate from image data captured by one camera, calculating the amount of positional misalignment of the disc-shaped substrate on a support member as the disc-shaped substrate is being transported during processing, and correcting the position such that the substrate can be located at the precise loading position. Isosceles right triangles, each having the radius of the disc-shaped substrate as one side, are generated from the coordinates of two places on edge data extracted from the image data and the radius on the edge data, and the coordinates of the center position of the disc-shaped substrate are detected by using the Pythagorean theorem.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: March 1, 2016
    Assignee: Rorze Corporation
    Inventors: Keiji Fujimoto, Yasuharu Yamamoto
  • Publication number: 20150287625
    Abstract: Provided is a position detecting device that is capable of precisely detecting the coordinates of the center of a disc-shaped substrate from image data captured by one camera, calculating the amount of positional misalignment of the disc-shaped substrate on a support member as the disc-shaped substrate is being transported during processing, and correcting the position such that the substrate can be located at the precise loading position. Isosceles right triangles, each having the radius of the disc-shaped substrate as one side, are generated from the coordinates of two places on edge data extracted from the image data and the radius on the edge data, and the coordinates of the center position of the disc-shaped substrate are detected by using the Pythagorean theorem.
    Type: Application
    Filed: October 23, 2013
    Publication date: October 8, 2015
    Inventors: Keiji Fujimoto, Yasuharu Yamamoto
  • Patent number: 8078409
    Abstract: An external quality control method, using an external quality control system which comprises an external quality control computer and a plurality of preprocessing devices connected to the external quality control computer via a network, comprising: performing preprocessing operations on preprocessing quality control samples, the preprocessing devices being adapted to prepare samples for measurement of target nucleic acid; measuring preprocessed preprocessing quality control samples to obtain measurement data; providing the measurement data to the external quality control computer over the network; storing the measurement data; and implementing an external quality control process based on the measurement data, is disclosed. An external quality control method for detection of nucleic acid, an external quality control method for preparation of calibration curve, an external quality control computer, a preprocessing device, and a nucleic acid detecting device are also disclosed.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: December 13, 2011
    Assignee: Sysmex Corporation
    Inventors: Masatoshi Yamasaki, Keiji Fujimoto
  • Publication number: 20080233593
    Abstract: A pseudo-tissue for quality control is described, which includes a nucleic acid component selected from the group consisting of a nucleic acid and a cell including a nucleic acid, and a gel for holding nucleic acid component.
    Type: Application
    Filed: April 30, 2008
    Publication date: September 25, 2008
    Inventors: Masatoshi Yamasaki, Keiji Fujimoto
  • Patent number: 7339234
    Abstract: An LDMOS transistor includes a gate insulation film formed on a semiconductor substrate, a gate electrode formed on the gate insulation film, a drain well of a first conductivity type formed in the substrate so as to include a gate region covered with the gate electrode, a channel well of a second conductivity type formed in the drain well in a partially overlapped relationship with the gate region, a source region of the first conductivity type formed in the channel well in an overlapping manner or adjacent with a side surface of the gate electrode, a medium-concentration drain region of the first conductivity type having an intermediate concentration level and formed in the drain well at a side opposing to the source region in a manner partially overlapping with the gate region, the medium-concentration drain region being formed with a separation from the channel well, a drain region of the first conductivity type formed in the medium-concentration drain region with a separation from the gate region, a low
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: March 4, 2008
    Assignee: Ricoh Company, Ltd.
    Inventor: Keiji Fujimoto
  • Patent number: 7242059
    Abstract: A semiconductor device includes a P-type semiconductor substrate, a P-channel DMOS transistor, a CMOS transistor. The P-channel DMOS transistor is disposed on the P-type semiconductor substrate and includes a drain formed of the P-type semiconductor substrate and a source formed in the P-type semiconductor substrate on a main surface of the P-type semiconductor substrate. The CMOS transistor is disposed on the P-type semiconductor substrate and includes a P-channel MOS transistor and an N-channel MOS transistor. The P-channel MOS transistor is formed in an N-type region formed in the P-type semiconductor substrate on the main surface of the P-type semiconductor substrate. The N-channel MOS transistor is formed in a P-type region formed in the P-type semiconductor substrate on the main surface of the P-type semiconductor substrate. The P-type region is electrically isolated from the P-type semiconductor substrate by the N-type region.
    Type: Grant
    Filed: February 3, 2004
    Date of Patent: July 10, 2007
    Assignee: Ricoh Company, Ltd.
    Inventors: Takaaki Negoro, Keiji Fujimoto, Takeshi Kimura
  • Publication number: 20070027635
    Abstract: An external quality control method, using an external quality control system which comprises an external quality control computer and a plurality of preprocessing devices connected to the external quality control computer via a network, comprising: performing preprocessing operations on preprocessing quality control samples, the preprocessing devices being adapted to prepare samples for measurement of target nucleic acid; measuring preprocessed preprocessing quality control samples to obtain measurement data; providing the measurement data to the external quality control computer over the network; storing the measurement data; and implementing an external quality control process based on the measurement data, is disclosed. An external quality control method for detection of nucleic acid, an external quality control method for preparation of calibration curve, an external quality control computer, a preprocessing device, and a nucleic acid detecting device are also disclosed.
    Type: Application
    Filed: July 25, 2006
    Publication date: February 1, 2007
    Inventors: Masatoshi Yamasaki, Keiji Fujimoto
  • Publication number: 20060197149
    Abstract: An LDMOS transistor includes a gate insulation film formed on a semiconductor substrate, a gate electrode formed on the gate insulation film, a drain well of a first conductivity type formed in the substrate so as to include a gate region covered with the gate electrode, a channel well of a second conductivity type formed in the drain well in a partially overlapped relationship with the gate region, a source region of the first conductivity type formed in the channel well in an overlapping manner or adjacent with a side surface of the gate electrode, a medium-concentration drain region of the first conductivity type having an intermediate concentration level and formed in the drain well at a side opposing to the source region in a manner partially overlapping with the gate region, the medium-concentration drain region being formed with a separation from the channel well, a drain region of the first conductivity type formed in the medium-concentration drain region with a separation from the gate region, a low
    Type: Application
    Filed: March 3, 2006
    Publication date: September 7, 2006
    Inventor: Keiji Fujimoto
  • Publication number: 20060084103
    Abstract: A pseudo-tissue for quality control is described, which includes a nucleic acid component selected from the group consisting of a nucleic acid and a cell including a nucleic acid, and a gel for holding nucleic acid component.
    Type: Application
    Filed: October 13, 2005
    Publication date: April 20, 2006
    Inventors: Masatoshi Yamasaki, Keiji Fujimoto
  • Publication number: 20060027864
    Abstract: An LDMOS transistor and a bipolar transistor with LDMOS structures are disclosed for suitable use in high withstand voltage device applications, among others. The LDMOS transistor includes a drain well region 21 formed in P-type substrate 1, and also formed therein spatially separated one another are a channel well region 23 and a medium concentration drain region 24 having an impurity concentration larger than that of drain well region 21, which are simultaneously formed having a large diffusion depth through thermal processing. A source 11s is formed in channel well region 23, while a drain 11d is formed in drain region 24 having an impurity concentration larger than that of drain region 24. In addition, a gate electrode 11g is formed over the well region, overlying the partially overlapped portions with well region 23 and drain region 24 and being separated from drain 11d.
    Type: Application
    Filed: October 6, 2005
    Publication date: February 9, 2006
    Inventors: Takaaki Negoro, Keiji Fujimoto
  • Patent number: 6979864
    Abstract: An LDMOS transistor and a bipolar transistor with LDMOS structures are disclosed for suitable use in high withstand voltage device applications, among others. The LDMOS transistor includes a drain well region 21 formed in P-type substrate 1, and also formed therein spatially separated one another are a channel well region 23 and a medium concentration drain region 24 having an impurity concentration larger than that of drain well region 21, which are simultaneously formed having a large diffusion depth through thermal processing. A source 11s is formed in channel well region 23, while a drain 11d is formed in drain region 24 having an impurity concentration larger than that of drain region 24. In addition, a gate electrode 11g is formed over the well region, overlying the partially overlapped portions with well region 23 and drain region 24 and being separated from drain 11d.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: December 27, 2005
    Assignee: Ricoh Company, Ltd.
    Inventors: Takaaki Negoro, Keiji Fujimoto
  • Publication number: 20050194639
    Abstract: An LDMOS transistor and a bipolar transistor with LDMOS structures are disclosed for suitable use in high withstand voltage device applications, among others. The LDMOS transistor includes a drain well region 21 formed in P-type substrate 1, and also formed therein spatially separated one another are a channel well region 23 and a medium concentration drain region 24 having an impurity concentration larger than that of drain well region 21, which are simultaneously formed having a large diffusion depth through thermal processing. A source 11s is formed in channel well region 23, while a drain 11d is formed in drain region 24 having an impurity concentration larger than that of drain region 24. In addition, a gate electrode 11g is formed over the well region, overlying the partially overlapped portions with well region 23 and drain region 24 and being separated from drain 11d.
    Type: Application
    Filed: April 27, 2005
    Publication date: September 8, 2005
    Inventors: Takaaki Negoro, Keiji Fujimoto
  • Patent number: 6911694
    Abstract: An LDMOS transistor and a bipolar transistor with LDMOS structures are disclosed for suitable use in high withstand voltage device applications, among others. The LDMOS transistor includes a drain well region 21 formed in P-type substrate 1, and also formed therein spatially separated one another are a channel well region 23 and a medium concentration drain region 24 having an impurity concentration larger than that of drain well region 21, which are simultaneously formed having a large diffusion depth through thermal processing. A source 11s is formed in channel well region 23, while a drain 11d is formed in drain region 24 having an impurity concentration larger than that of drain region 24. In addition, a gate electrode 11g is formed over the well region, overlying the partially overlapped portions with well region 23 and drain region 24 and being separated from drain 11d.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: June 28, 2005
    Assignee: Ricoh Company, Ltd.
    Inventors: Takaaki Negoro, Keiji Fujimoto
  • Publication number: 20040227183
    Abstract: A semiconductor device includes a P-type semiconductor substrate, a P-channel DMOS transistor, a CMOS transistor. The P-channel DMOS transistor is disposed on the P-type semiconductor substrate and includes a drain formed of the P-type semiconductor substrate and a source formed in the P-type semiconductor substrate on a main surface of the P-type semiconductor substrate. The CMOS transistor is disposed on the P-type semiconductor substrate and includes a P-channel MOS transistor and an N-channel MOS transistor. The P-channel MOS transistor is formed in an N-type region formed in the P-type semiconductor substrate on the main surface of the P-type semiconductor substrate. The N-channel MOS transistor is formed in a P-type region formed in the P-type semiconductor substrate on the main surface of the P-type semiconductor substrate. The P-type region is electrically isolated from the P-type semiconductor substrate by the N-type region.
    Type: Application
    Filed: February 3, 2004
    Publication date: November 18, 2004
    Inventors: Takaaki Negoro, Keiji Fujimoto, Takeshi Kimura