Patents by Inventor Keiji Hosotani

Keiji Hosotani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10868037
    Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnecting layer; a first signal line; a first memory cell that stores first information between the first interconnecting layer and the first signal line; second to fourth interconnecting layers provided above the first interconnecting layer; fifth to seventh interconnecting layers disposed apart from the second to fourth interconnecting layers; a second signal line coupled to the first signal line; a third signal line coupled to the first and second signal lines and the sixth interconnecting layer; and, first to fifth transistors.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: December 15, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Fumitaka Arai, Masakazu Goto, Masaki Kondo, Keiji Hosotani, Nobuyuki Momo
  • Publication number: 20200303400
    Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnecting layer; a first signal line; a first memory cell that stores first information between the first interconnecting layer and the first signal line; second to fourth interconnecting layers provided above the first interconnecting layer; fifth to seventh interconnecting layers disposed apart from the second to fourth interconnecting layers; a second signal line coupled to the first signal line; a third signal line coupled to the first and second signal lines and the sixth interconnecting layer; and, first to fifth transistors.
    Type: Application
    Filed: July 3, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Fumitaka ARAI, Masakazu GOTO, Masaki KONDO, Keiji HOSOTANI, Nobuyuki MOMO
  • Publication number: 20200286828
    Abstract: According to one embodiment, a semiconductor memory device includes: a first semiconductor layer including first to third portions which are arranged along a first direction and differ in position from one another in a second direction; a conductive layer including a fourth portion extending in the second direction and a fifth portion extending in the first direction; a first insulating layer between the fourth portion and the first semiconductor layer and between the fifth portion and the first semiconductor layer; a first contact plug coupled to the fourth portion; a second contact plug coupled to the first semiconductor layer in a region where the first insulating layer is formed; a first interconnect; and a first memory cell apart from the fifth portion in the first direction and storing information between the semiconductor layer and the first interconnect.
    Type: Application
    Filed: September 9, 2019
    Publication date: September 10, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keiji HOSOTANI, Fumitaka ARAI, Keisuke NAKATSUKA, Nobuyuki MOMO, Motohiko FUJIMATSU
  • Publication number: 20200176033
    Abstract: According to one embodiment, a semiconductor memory device includes: a conductive layer including a first portion and a second portion electrically coupled to the first portion; a first contact plug electrically coupled to the first portion; a first semiconductor layer; a first insulating layer between the second portion and the first semiconductor layer, and between the first portion and the first semiconductor layer; a second contact plug coupled to the first semiconductor layer in a region in which the first insulating layer is formed; a first interconnect; and a first memory cell apart from the second portion in the second direction and storing information between the first semiconductor layer and the first interconnect.
    Type: Application
    Filed: September 5, 2019
    Publication date: June 4, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keiji HOSOTANI, Fumitaka ARAI, Keisuke NAKATSUKA
  • Publication number: 20200135242
    Abstract: According to one embodiment, a semiconductor memory device includes: first to fifth interconnects; a semiconductor layer having one end located between the fourth interconnect and the fifth interconnect and other end connected to the first interconnect; a memory cell; a conductive layer having one end connected to the second interconnect and other end connected to the semiconductor layer; a first insulating layer provided to extend between the third and fourth interconnects and the semiconductor layer, and between the fifth interconnect and the conductive layer; an oxide semiconductor layer provided to extend between the fourth and fifth interconnects and the first insulating layer; and a second insulating layer provided to extend between the fourth and fifth interconnects and the oxide semiconductor layer.
    Type: Application
    Filed: July 3, 2019
    Publication date: April 30, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Fumitaka ARAI, Keiji HOSOTANI, Nobuyuki MOMO
  • Patent number: 10622545
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, a first non-magnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the first magnetic layer and having a fixed magnetization direction and provided on the first magnetic layer. The second magnetic layer includes a non-magnetic metal including at least one of Mo (molybdenum), Ta (tantalum), W (tungsten), Hf (hafnium), Nb (niobium) and Ti (titanium).
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: April 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masaru Toko, Keiji Hosotani, Hisanori Aikawa, Tatsuya Kishi
  • Patent number: 10410704
    Abstract: According to one embodiment, a memory includes a first MTJ element having a first area along a first plane; and second MTJ elements each having a second area along the first plane. The second area is larger than or equal to twice the first area and smaller than or equal to five times the first area. Each of the second MTJ elements includes a first ferromagnet, a second ferromagnet, and a first nonmagnet. Respective magnetizations of respective first ferromagnets of the second MTJ elements are oriented along a first direction. Respective magnetizations of respective second ferromagnets of the second MTJ elements are oriented along a second direction. One of the second MTJ elements is coupled to another one of the second MTJ elements in series or in parallel.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: September 10, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keiji Hosotani, Tatsuya Kishi, Akira Katayama
  • Patent number: 10311929
    Abstract: According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: June 4, 2019
    Assignees: TOSHIBA MEMORY CORPORATION, SK HYNIX INC.
    Inventors: Hisanori Aikawa, Tatsuya Kishi, Keisuke Nakatsuka, Satoshi Inaba, Masaru Toko, Keiji Hosotani, Jae Yun Yi, Hong Ju Suh, Se Dong Kim
  • Publication number: 20180277744
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, a first non-magnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the first magnetic layer and having a fixed magnetization direction and provided on the first magnetic layer. The second magnetic layer includes a non-magnetic metal including at least one of Mo (molybdenum), Ta (tantalum), W (tungsten), Hf (hafnium), Nb (niobium) and Ti (titanium).
    Type: Application
    Filed: September 12, 2017
    Publication date: September 27, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Masaru TOKO, Keiji HOSOTANI, Hisanori AIKAWA, Tatsuya KISHI
  • Publication number: 20180277183
    Abstract: According to one embodiment, a memory includes a first MTJ element having a first area along a first plane; and second MTJ elements each having a second area along the first plane. The second area is larger than or equal to twice the first area and smaller than or equal to five times the first area. Each of the second MTJ elements includes a first ferromagnet, a second ferromagnet, and a first nonmagnet. Respective magnetizations of respective first ferromagnets of the second MTJ elements are oriented along a first direction. Respective magnetizations of respective second ferromagnets of the second MTJ elements are oriented along a second direction. One of the second MTJ elements is coupled to another one of the second MTJ elements in series or in parallel.
    Type: Application
    Filed: September 12, 2017
    Publication date: September 27, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keiji HOSOTANI, Tatsuya KISHI, Akira KATAYAMA
  • Publication number: 20180102156
    Abstract: According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.
    Type: Application
    Filed: December 8, 2017
    Publication date: April 12, 2018
    Applicants: TOSHIBA MEMORY CORPORATION, SK HYNIX INC.
    Inventors: Hisanori AIKAWA, Tatsuya KISHI, Keisuke NAKATSUKA, Satoshi INABA, Masaru TOKO, Keiji HOSOTANI, Jae Yun YI, Hong Ju SUH, Se Dong KIM
  • Patent number: 9799383
    Abstract: According to one embodiment, the magnetic memory device includes a first magnetoresistive element and a second magnetoresistive element which are adjacent to each other. Each of the first and second magnetoresistive elements includes a first magnetic layer, a first non-magnetic later on the first magnetic layer, a second magnetic layer on the first non-magnetic layer, a second non-magnetic layer on the second magnetic layer, and a third magnetic layer on the second non-magnetic layer. Furthermore, the magnetic memory device further includes a fourth magnetic layer being in contact with the first and second magnetoresistive elements or in contact with conductive layers on the first and second magnetoresistive elements.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: October 24, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keiji Hosotani, Tatsuya Kishi
  • Publication number: 20170263296
    Abstract: According to one embodiment, the magnetic memory device includes a first magnetoresistive element and a second magnetoresistive element which are adjacent to each other. Each of the first and second magnetoresistive elements includes a first magnetic layer, a first non-magnetic later on the first magnetic layer, a second magnetic layer on the first non-magnetic layer, a second non-magnetic layer on the second magnetic layer, and a third magnetic layer on the second non-magnetic layer. Furthermore, the magnetic memory device further includes a fourth magnetic layer being in contact with the first and second magnetoresistive elements or in contact with conductive layers on the first and second magnetoresistive elements.
    Type: Application
    Filed: September 9, 2016
    Publication date: September 14, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiji HOSOTANI, Tatsuya KISHI
  • Publication number: 20170256706
    Abstract: According to one embodiment, a magnetic storage device includes a first and a second magnetoresistive effect element, which are disposed in an arrangement pattern including a plurality of arrangement areas, and in each of which a second ferromagnetic layer and a third ferromagnetic layer are antiferromagnetically coupled. A magnetization orientation of the third ferromagnetic layer of the first magnetoresistive effect element is antiparallel to a magnetization orientation of the third ferromagnetic layer of the second magnetoresistive effect element. The first magnetoresistive effect element is disposed in an arrangement area randomly positioned with respect to an arrangement area in which the second magnetoresistive effect element is disposed.
    Type: Application
    Filed: September 9, 2016
    Publication date: September 7, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaru TOKO, Keiji HOSOTANI, Hisanori AIKAWA, Tatsuya KISHI
  • Patent number: 9653182
    Abstract: According to one embodiment, a testing method of a memory device includes annealing the memory device, the memory device including a memory element; performing, after the annealing, to the memory element a process which sets a first magnetization orientation of a first ferromagnetic layer to be antiparallel to a second magnetization orientation of the second ferromagnetic layer; reading, after the performing of the process, data from the memory element; and determining the memory element as defective due to the second magnetization orientation being parallel to a third magnetization orientation of a third ferromagnetic layer, when data represented by the first magnetization orientation being antiparallel to the second magnetization orientation differs from the read data.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: May 16, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaru Toko, Keiji Hosotani, Hisanori Aikawa, Tatsuya Kishi
  • Patent number: 9269889
    Abstract: According to one embodiment, a semiconductor memory device comprises a memory cell array. The memory cell array has a plurality of magnetic tunnel junction (MTJ) elements. Each of the MTJ elements has a first magnetic layer, a second magnetic layer and a non-magnetic layer therebetween, and a hard mask layer is arranged above the second magnetic layer. The plurality of MTJ elements have a first MTJ element having a first hard mask layer and a second MTJ element having a second hard mask layer, and a dimension of, the first hard mask layer is greater than that of the second hard mask layer.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: February 23, 2016
    Inventors: Keiji Hosotani, Sumio Ikegawa, Tatsuya Kishi
  • Publication number: 20150263264
    Abstract: According to one embodiment, a semiconductor memory device comprises a memory cell array. The memory cell array has a plurality of magnetic tunnel junction (MTJ) elements. Each of the MTJ elements has a first magnetic layer, a second magnetic layer and a non-magnetic layer therebetween, and a hard mask layer is arranged above the second magnetic layer. The plurality of MTJ elements have a first MTJ element having a first hard mask layer and a second MTJ element having a second hard mask layer, and a dimension of, the first hard mask layer is greater than that of the second hard mask layer.
    Type: Application
    Filed: September 5, 2014
    Publication date: September 17, 2015
    Inventors: Keiji HOSOTANI, Sumio IKEGAWA, Tatsuya KISHI
  • Patent number: 8786038
    Abstract: A semiconductor storage device according to the present embodiment includes a selection element formed on a surface of a semiconductor substrate. A lower electrode is connected to the selection element. A magnetic tunnel junction element is provided on the lower electrode. An upper electrode is provided on the magnetic tunnel junction element. A growth layer is provided on the upper electrode and is composed of a conductive material and has a larger area than the upper electrode when viewed from above the surface of the semiconductor substrate. A wiring line is provided on the growth layer.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: July 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Hosotani, Hiroyuki Kanaya
  • Patent number: 8716818
    Abstract: According to one embodiment, a magnetoresistive element includes a storage layer having a variable and perpendicular magnetization, a tunnel barrier layer on the storage layer, a reference layer having an invariable and perpendicular magnetization on the tunnel barrier layer, a hard mask layer on the reference layer, and a sidewall spacer layer on sidewalls of the reference layer and the hard mask layer. An in-plane size of the reference layer is smaller than an in-plane size of the storage layer. A difference between the in-plane sizes of the storage layer and the reference layer is 2 nm or less. The sidewall spacer layer includes a material selected from a group of a diamond, DLC, BN, SiC, B4C, Al2O3 and AlN.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: May 6, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masatoshi Yoshikawa, Satoshi Seto, Hideaki Harakawa, Jyunichi Ozeki, Tatsuya Kishi, Keiji Hosotani
  • Patent number: 8604569
    Abstract: A magnetoresistive element includes a first electrode layer, a first fixed layer provided on the first electrode layer and having a fixed magnetization direction, a first intermediate layer provided on the first fixed layer and made of a metal oxide, a free layer provided on the first intermediate layer and having a variable magnetization direction, and a second electrode layer provided on the free layer. At least one of the first electrode layer and the second electrode layer contains a conductive metal oxide.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: December 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Hosotani, Yoshiaki Asao