Patents by Inventor Keiji Hosotani

Keiji Hosotani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10410704
    Abstract: According to one embodiment, a memory includes a first MTJ element having a first area along a first plane; and second MTJ elements each having a second area along the first plane. The second area is larger than or equal to twice the first area and smaller than or equal to five times the first area. Each of the second MTJ elements includes a first ferromagnet, a second ferromagnet, and a first nonmagnet. Respective magnetizations of respective first ferromagnets of the second MTJ elements are oriented along a first direction. Respective magnetizations of respective second ferromagnets of the second MTJ elements are oriented along a second direction. One of the second MTJ elements is coupled to another one of the second MTJ elements in series or in parallel.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: September 10, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keiji Hosotani, Tatsuya Kishi, Akira Katayama
  • Patent number: 10311929
    Abstract: According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: June 4, 2019
    Assignees: TOSHIBA MEMORY CORPORATION, SK HYNIX INC.
    Inventors: Hisanori Aikawa, Tatsuya Kishi, Keisuke Nakatsuka, Satoshi Inaba, Masaru Toko, Keiji Hosotani, Jae Yun Yi, Hong Ju Suh, Se Dong Kim
  • Publication number: 20180277744
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, a first non-magnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the first magnetic layer and having a fixed magnetization direction and provided on the first magnetic layer. The second magnetic layer includes a non-magnetic metal including at least one of Mo (molybdenum), Ta (tantalum), W (tungsten), Hf (hafnium), Nb (niobium) and Ti (titanium).
    Type: Application
    Filed: September 12, 2017
    Publication date: September 27, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Masaru TOKO, Keiji HOSOTANI, Hisanori AIKAWA, Tatsuya KISHI
  • Publication number: 20180277183
    Abstract: According to one embodiment, a memory includes a first MTJ element having a first area along a first plane; and second MTJ elements each having a second area along the first plane. The second area is larger than or equal to twice the first area and smaller than or equal to five times the first area. Each of the second MTJ elements includes a first ferromagnet, a second ferromagnet, and a first nonmagnet. Respective magnetizations of respective first ferromagnets of the second MTJ elements are oriented along a first direction. Respective magnetizations of respective second ferromagnets of the second MTJ elements are oriented along a second direction. One of the second MTJ elements is coupled to another one of the second MTJ elements in series or in parallel.
    Type: Application
    Filed: September 12, 2017
    Publication date: September 27, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keiji HOSOTANI, Tatsuya KISHI, Akira KATAYAMA
  • Publication number: 20180102156
    Abstract: According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.
    Type: Application
    Filed: December 8, 2017
    Publication date: April 12, 2018
    Applicants: TOSHIBA MEMORY CORPORATION, SK HYNIX INC.
    Inventors: Hisanori AIKAWA, Tatsuya KISHI, Keisuke NAKATSUKA, Satoshi INABA, Masaru TOKO, Keiji HOSOTANI, Jae Yun YI, Hong Ju SUH, Se Dong KIM
  • Patent number: 9799383
    Abstract: According to one embodiment, the magnetic memory device includes a first magnetoresistive element and a second magnetoresistive element which are adjacent to each other. Each of the first and second magnetoresistive elements includes a first magnetic layer, a first non-magnetic later on the first magnetic layer, a second magnetic layer on the first non-magnetic layer, a second non-magnetic layer on the second magnetic layer, and a third magnetic layer on the second non-magnetic layer. Furthermore, the magnetic memory device further includes a fourth magnetic layer being in contact with the first and second magnetoresistive elements or in contact with conductive layers on the first and second magnetoresistive elements.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: October 24, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keiji Hosotani, Tatsuya Kishi
  • Publication number: 20170263296
    Abstract: According to one embodiment, the magnetic memory device includes a first magnetoresistive element and a second magnetoresistive element which are adjacent to each other. Each of the first and second magnetoresistive elements includes a first magnetic layer, a first non-magnetic later on the first magnetic layer, a second magnetic layer on the first non-magnetic layer, a second non-magnetic layer on the second magnetic layer, and a third magnetic layer on the second non-magnetic layer. Furthermore, the magnetic memory device further includes a fourth magnetic layer being in contact with the first and second magnetoresistive elements or in contact with conductive layers on the first and second magnetoresistive elements.
    Type: Application
    Filed: September 9, 2016
    Publication date: September 14, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiji HOSOTANI, Tatsuya KISHI
  • Publication number: 20170256706
    Abstract: According to one embodiment, a magnetic storage device includes a first and a second magnetoresistive effect element, which are disposed in an arrangement pattern including a plurality of arrangement areas, and in each of which a second ferromagnetic layer and a third ferromagnetic layer are antiferromagnetically coupled. A magnetization orientation of the third ferromagnetic layer of the first magnetoresistive effect element is antiparallel to a magnetization orientation of the third ferromagnetic layer of the second magnetoresistive effect element. The first magnetoresistive effect element is disposed in an arrangement area randomly positioned with respect to an arrangement area in which the second magnetoresistive effect element is disposed.
    Type: Application
    Filed: September 9, 2016
    Publication date: September 7, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaru TOKO, Keiji HOSOTANI, Hisanori AIKAWA, Tatsuya KISHI
  • Patent number: 9653182
    Abstract: According to one embodiment, a testing method of a memory device includes annealing the memory device, the memory device including a memory element; performing, after the annealing, to the memory element a process which sets a first magnetization orientation of a first ferromagnetic layer to be antiparallel to a second magnetization orientation of the second ferromagnetic layer; reading, after the performing of the process, data from the memory element; and determining the memory element as defective due to the second magnetization orientation being parallel to a third magnetization orientation of a third ferromagnetic layer, when data represented by the first magnetization orientation being antiparallel to the second magnetization orientation differs from the read data.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: May 16, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaru Toko, Keiji Hosotani, Hisanori Aikawa, Tatsuya Kishi
  • Patent number: 9269889
    Abstract: According to one embodiment, a semiconductor memory device comprises a memory cell array. The memory cell array has a plurality of magnetic tunnel junction (MTJ) elements. Each of the MTJ elements has a first magnetic layer, a second magnetic layer and a non-magnetic layer therebetween, and a hard mask layer is arranged above the second magnetic layer. The plurality of MTJ elements have a first MTJ element having a first hard mask layer and a second MTJ element having a second hard mask layer, and a dimension of, the first hard mask layer is greater than that of the second hard mask layer.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: February 23, 2016
    Inventors: Keiji Hosotani, Sumio Ikegawa, Tatsuya Kishi
  • Publication number: 20150263264
    Abstract: According to one embodiment, a semiconductor memory device comprises a memory cell array. The memory cell array has a plurality of magnetic tunnel junction (MTJ) elements. Each of the MTJ elements has a first magnetic layer, a second magnetic layer and a non-magnetic layer therebetween, and a hard mask layer is arranged above the second magnetic layer. The plurality of MTJ elements have a first MTJ element having a first hard mask layer and a second MTJ element having a second hard mask layer, and a dimension of, the first hard mask layer is greater than that of the second hard mask layer.
    Type: Application
    Filed: September 5, 2014
    Publication date: September 17, 2015
    Inventors: Keiji HOSOTANI, Sumio IKEGAWA, Tatsuya KISHI
  • Patent number: 8786038
    Abstract: A semiconductor storage device according to the present embodiment includes a selection element formed on a surface of a semiconductor substrate. A lower electrode is connected to the selection element. A magnetic tunnel junction element is provided on the lower electrode. An upper electrode is provided on the magnetic tunnel junction element. A growth layer is provided on the upper electrode and is composed of a conductive material and has a larger area than the upper electrode when viewed from above the surface of the semiconductor substrate. A wiring line is provided on the growth layer.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: July 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Hosotani, Hiroyuki Kanaya
  • Patent number: 8716818
    Abstract: According to one embodiment, a magnetoresistive element includes a storage layer having a variable and perpendicular magnetization, a tunnel barrier layer on the storage layer, a reference layer having an invariable and perpendicular magnetization on the tunnel barrier layer, a hard mask layer on the reference layer, and a sidewall spacer layer on sidewalls of the reference layer and the hard mask layer. An in-plane size of the reference layer is smaller than an in-plane size of the storage layer. A difference between the in-plane sizes of the storage layer and the reference layer is 2 nm or less. The sidewall spacer layer includes a material selected from a group of a diamond, DLC, BN, SiC, B4C, Al2O3 and AlN.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: May 6, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masatoshi Yoshikawa, Satoshi Seto, Hideaki Harakawa, Jyunichi Ozeki, Tatsuya Kishi, Keiji Hosotani
  • Patent number: 8604569
    Abstract: A magnetoresistive element includes a first electrode layer, a first fixed layer provided on the first electrode layer and having a fixed magnetization direction, a first intermediate layer provided on the first fixed layer and made of a metal oxide, a free layer provided on the first intermediate layer and having a variable magnetization direction, and a second electrode layer provided on the free layer. At least one of the first electrode layer and the second electrode layer contains a conductive metal oxide.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: December 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Hosotani, Yoshiaki Asao
  • Patent number: 8592928
    Abstract: According to one embodiment, a magnetic random access memory includes a selection element formed on a semiconductor substrate, an interlayer dielectric film formed above the selection element, a contact layer formed in the interlayer dielectric film, and electrically connected to the selection element, a lower electrode layer made of a metal material, and electrically connected to the contact layer, a metal oxide insulating film made of an oxide of the metal material, and surrounding a side surface of the lower electrode layer, a magnetoresistive element formed on the lower electrode layer, an upper electrode layer formed on the magnetoresistive element, a sidewall insulating film formed on a side surface of the magnetoresistive element and a side surface of the upper electrode layer, and a bit line electrically connected to the upper electrode layer.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: November 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Hosotani, Hiroyuki Kanaya, Takeshi Kajiyama
  • Patent number: 8553450
    Abstract: A first magnetic layer has a magnetization fixed along one direction. A first nonmagnetic layer on the first magnetic layer functions as a first tunnel barrier. A second magnetic layer on the first nonmagnetic layer has a magnetization whose direction can be reversed by spin transfer current injection. A second nonmagnetic layer on the second magnetic layer functions as a second tunnel barrier. A third magnetic layer on the second nonmagnetic layer has a magnetization whose direction can be reversed by spin transfer through current injection at a current density different from the second magnetic layer. First magnetic, first nonmagnetic layer, and second magnetic layers exhibit a first magnetoresistive effect. Second magnetic, second nonmagnetic, and third magnetic layers exhibit a second magnetoresistive effect. A magnetoresistive effect element records and reads out data of at least three levels based on a synthetic resistance from the first and second magnetoresistive effects.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: October 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Hosotani, Masahiko Nakayama
  • Publication number: 20130001652
    Abstract: According to one embodiment, a magnetoresistive element includes a storage layer having a variable and perpendicular magnetization, a tunnel barrier layer on the storage layer, a reference layer having an invariable and perpendicular magnetization on the tunnel barrier layer, a hard mask layer on the reference layer, and a sidewall spacer layer on sidewalls of the reference layer and the hard mask layer. An in-plane size of the reference layer is smaller than an in-plane size of the storage layer. A difference between the in-plane sizes of the storage layer and the reference layer is 2 nm or less. The sidewall spacer layer includes a material selected from a group of a diamond, DLC, BN, SiC, B4C, Al2O3 and AlN.
    Type: Application
    Filed: March 23, 2012
    Publication date: January 3, 2013
    Inventors: Masatoshi Yoshikawa, Satoshi Seto, Hideaki Harakawa, Jyunichi Ozeki, Tatsuya Kishi, Keiji Hosotani
  • Patent number: 8173447
    Abstract: A magnetoresistive element includes: a magnetization free layer having a first plane and a second plane located on the opposite side from the first plane, and having a variable magnetization direction; a magnetization pinned layer provided on the first plane side of the magnetization free layer, and having a pinned magnetization direction; a first tunnel barrier layer provided between the magnetization free layer and the magnetization pinned layer; a second tunnel barrier layer provided on the second plane of the magnetization free layer; and a non-magnetic layer provided on a plane on the opposite side of the second tunnel barrier layer from the magnetization free layer. The magnetization direction of the magnetization free layer is variable by applying current between the magnetization pinned layer and the non-magnetic layer, and a resistance ratio between the first tunnel barrier layer and the second tunnel barrier layer is in a range of 1:0.25 to 1:4.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: May 8, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomomasa Ueda, Hisanori Aikawa, Masatoshi Yoshikawa, Naoharu Shimomura, Masahiko Nakayama, Sumio Ikegawa, Keiji Hosotani, Makoto Nagamine
  • Publication number: 20120068283
    Abstract: A semiconductor storage device according to the present embodiment includes a selection element formed on a surface of a semiconductor substrate. A lower electrode is connected to the selection element. A magnetic tunnel junction element is provided on the lower electrode. An upper electrode is provided on the magnetic tunnel junction element. A growth layer is provided on the upper electrode and is composed of a conductive material and has a larger area than the upper electrode when viewed from above the surface of the semiconductor substrate. A wiring line is provided on the growth layer.
    Type: Application
    Filed: September 12, 2011
    Publication date: March 22, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiji HOSOTANI, Hiroyuki Kanaya
  • Publication number: 20120068286
    Abstract: According to one embodiment, a magnetic random access memory includes a selection element formed on a semiconductor substrate, an interlayer dielectric film formed above the selection element, a contact layer formed in the interlayer dielectric film, and electrically connected to the selection element, a lower electrode layer made of a metal material, and electrically connected to the contact layer, a metal oxide insulating film made of an oxide of the metal material, and surrounding a side surface of the lower electrode layer, a magnetoresistive element formed on the lower electrode layer, an upper electrode layer formed on the magnetoresistive element, a sidewall insulating film formed on a side surface of the magnetoresistive element and a side surface of the upper electrode layer, and a bit line electrically connected to the upper electrode layer.
    Type: Application
    Filed: September 20, 2011
    Publication date: March 22, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiji Hosotani, Hiroyuki Kanaya, Takeshi Kajiyama