Patents by Inventor Keiji Takaoka

Keiji Takaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6653660
    Abstract: A vertical cavity-type semiconductor light-emitting device comprises a first semiconductor distributed Bragg reflector type mirror formed on a substrate, a first semiconductor layer formed on the first semiconductor distributed Bragg reflector type mirror and including at least an active layer which becomes an emission layer, a second semiconductor distributed Bragg reflector type mirror formed on the first semiconductor layer and including Al as a configuration element, and a second semiconductor layer including InxGa1−xP (0≦x≦1) layer provided on the second semiconductor distributed Bragg reflector type mirror.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: November 25, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keiji Takaoka
  • Publication number: 20030183837
    Abstract: A low-cost high-property optical semiconductor element for a long wavelength is provided, using a GaAs substrate. The optical semiconductor element comprises a substrate of GaAs having a first surface and a second surface opposite to each other, a buffer layer of InjGa1−jAs1−kNk (0≦j≦1, 0.002≦k≦0.05) formed on the first surface of the substrate, a first conductive type clad layer formed on the buffer layer, an active layer formed on the first conductive type clad layer and comprising a well layer of InzGa1−zAs (0≦z≦1), the well layer having a smaller bandgap than the first conductive type clad layer, the active layer having a thickness of more than its critical thickness for the substrate based upon equilibrium theories, and a second conductive type clad layer formed on the active layer and having a larger bandgap than the well layer.
    Type: Application
    Filed: March 28, 2003
    Publication date: October 2, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiro Kushibe, Yasuo Ohba, Rei Hashimoto, Keiji Takaoka
  • Publication number: 20030063649
    Abstract: A semiconductor surface light-emitting device comprises, in a multi-layered structure formed on a substrate, a light-emitting part surrounded by a groove or grooves, provided with an active layer, a vertical cavity and a current aperture, a peripheral part external to the grooves, and a connecting portion connecting the light-emitting part with the peripheral part. There is provided an empty space or a high-resistance region on the upper part of this multi-layered connecting portion, which includes at least the current aperture formed layer or the active layer. This configuration effectively eliminates a path for a leakage current flowing into the peripheral part from the light-emitting part.
    Type: Application
    Filed: September 26, 2002
    Publication date: April 3, 2003
    Inventors: Mizunori Ezaki, Keiji Takaoka
  • Publication number: 20020134987
    Abstract: A resonant-cavity light-emitting diode includes a semiconductor light-emitting layer sandwiched between an under and an upper semiconductor distributed Bragg reflector mirror layer, which are formed on the substrate, a light extracting section formed on the upper semiconductor distributed Bragg reflector mirror layer and having an opening to extract light from the semiconductor light-emitting layer, and a groove formed by removing portions of the semiconductor light-emitting layer, under and upper semiconductor distributed Bragg reflector mirror layers which lie in a peripheral portion of the opening of the light extraction section and reach the under semiconductor distributed Bragg reflector mirror layer, the inner wall of the groove being formed to reflect part of light emitted from the semiconductor light-emitting layer into the groove.
    Type: Application
    Filed: March 8, 2002
    Publication date: September 26, 2002
    Inventor: Keiji Takaoka
  • Publication number: 20020038869
    Abstract: A vertical cavity-type semiconductor light-emitting device comprises a first semiconductor distributed Bragg reflector type mirror formed on a substrate, a first semiconductor layer formed on the first semiconductor distributed Bragg reflector type mirror and including at least an active layer which becomes an emission layer, a second semiconductor distributed Bragg reflector type mirror formed on the first semiconductor layer and including Al as a configuration element, and a second semiconductor layer including InxGa1−xP (0≦x≦1) layer provided on the second semiconductor distributed Bragg reflector type mirror.
    Type: Application
    Filed: September 24, 2001
    Publication date: April 4, 2002
    Inventor: Keiji Takaoka
  • Patent number: 5970081
    Abstract: A grating coupled surface emitting laser has a diffraction grating of a second or higher order for guided-mode light part of a waveguide region, and extract a beam in a direction perpendicular to the waveguide region. By narrowing a stripe of the waveguide region around the center, the phase of the diffraction grating is shifted to attain a Gaussian distribution for radiation-mode light in a cross section along the waveguiding direction.
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: October 19, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuzo Hirayama, Masahisa Funemizu, Masaki Tohyama, Motoyasu Morinaga, Keiji Takaoka, Kazuhiro Inoue, Makoto Ohashi
  • Patent number: 5822349
    Abstract: This invention is a semiconductor device including a p-type InP substrate having a mesa stripe in which at least an active layer and an n-type cladding layer are formed, and a semiconductor layer so formed as to bury the side surfaces of the mesa stripe and having at least an n-type current blocking layer and a p-type current blocking layer, wherein the n-type current blocking layer contains approximately 8.times.10.sup.17 cm.sup.-3 or more of Se as an impurity and the n-type current blocking layer and the n-type cladding layer are not contacting each other.
    Type: Grant
    Filed: March 12, 1996
    Date of Patent: October 13, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Takaoka, Mitsuhiro Kushibe, Toshihide Izumiya, Yoshihiro Kokubun
  • Patent number: 5434426
    Abstract: Disclosed herein is an optical interconnection device having a light source, a plurality of optical interconnecting elements, and a light-receiving element. The optical interconnecting elements are located on an output side of the light source. Each of the elements has first and second major surfaces and comprises an integral unit made of an optical semiconductor element and a grating lens having concentric annular grooves and concentric annular projections, and two electrodes formed on the first and second major surfaces, respectively. The optical semiconductor element and grating lens of each optical interconnecting element are formed on the first major surface, for emitting or receiving light. The light-receiving element is located on an output side of the optical interconnecting elements. The optical interconnecting elements are arranged at substantially regular intervals, each positioned such that the semiconductor element and the grating lens face to the same direction.
    Type: Grant
    Filed: September 10, 1993
    Date of Patent: July 18, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideto Furuyama, Hiroshi Hamasaki, Mitsuhiro Kushibe, Katsuji Kaminishi, Tamon Kobayashi, Keiji Takaoka
  • Patent number: 5001335
    Abstract: Disclosed are an avalanche photodiode and a manufacturing method thereof. An n.sup.- -type InGaAs light absorption layer and n.sup.- -type InP window layer are formed on an n-type InP substrate by crystal growth, in the order mentioned. A depression is formed in a selected surface portion of the window layer, and n-type impurities are doped into the bottom of the depression, to thereby form an n-type high concentration region. Further, n.sup.- -type crystal-grown InP layer is formed in the depression in such a way as to fill the depression. A guard ring is formed around the depression by the doping of p-type impurities. By doping p-type impurities into the window layer, a p-type high concentration region is formed in the window layer in a manner completely surrounding the interface between the n-type high concentration region and the crystal-grown InP layer. The n-type and p-type high concentration regions define a junction serving as a light-receiving region.
    Type: Grant
    Filed: December 29, 1989
    Date of Patent: March 19, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Takaoka, Tetsuo Sadamasa, Motoyasu Morinaga, Nobuo Suzuki, Kenji Matsumoto