Patents by Inventor Keiji Wada

Keiji Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SILICON CARBIDE SEMICONDUCTOR DEVICE
    Publication number: 20160079349
    Abstract: A silicon carbide semiconductor device includes a silicon carbide layer, an element region including a semiconductor element portion formed in the silicon carbide layer, a JTE region (first electric field relaxing region), an insulating film disposed on a first main surface and covering the JTE region, and a pad electrode electrically connected to the JTE region. The pad electrode includes an extension portion extending from an end of the JTE region close to the element region in a peripheral direction from the element region toward the JTE region, the extension portion being disposed on the insulating film. The extension portion overlies at least a portion of the JTE region.
    Type: Application
    Filed: November 19, 2015
    Publication date: March 17, 2016
    Inventors: Keiji Wada, Toru Hiyoshi, Masaki Furumai, Mitsuhiko Sakai, Kosuke Uchida
  • Silicon carbide semiconductor device
    Patent number: 9276105
    Abstract: A silicon carbide semiconductor device includes an element region and a guard ring region. A semiconductor element is provided in the element region. The guard ring region surrounds the element region in a plan view and has a first conductivity type. The semiconductor element includes a drift region having a second conductivity type different from the first conductivity type. The guard ring region includes a linear region and a curvature region continuously connected to the linear region. A value obtained by dividing a radius of curvature of an inner circumference portion of the curvature region by a thickness of the drift region is not less than 5 and not more than 10. Accordingly, there can be provided a silicon carbide semiconductor device capable of improving a breakdown voltage while suppressing decrease of on-state current.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: March 1, 2016
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shunsuke Yamada, Toru Hiyoshi, Takeyoshi Masuda, Keiji Wada
  • Silicon carbide semiconductor device and method for manufacturing same
    Patent number: 9276106
    Abstract: A silicon carbide film includes a first range having a first breakdown voltage holding layer, a charge compensation region, a first junction terminal region, and a first guard ring region. The silicon carbide film includes a second range having a second breakdown voltage holding layer, a channel forming region, and a source region. The first and second breakdown voltage holding layers constitutes a breakdown voltage holding region having a thickness in an element portion. When voltage is applied to attain a maximum electric field strength of 0.4 MV/cm or more in the breakdown voltage holding region during an OFF state, a maximum electric field strength in the second range within the element portion is configured to be less than ? of a maximum electric field strength in the first range.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: March 1, 2016
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Toru Hiyoshi
  • METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
    Publication number: 20160056041
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes the steps of preparing a silicon carbide substrate, forming a first electrode on the silicon carbide substrate, establishing ohmic contact between the silicon carbide substrate and the first electrode by irradiating the first electrode with laser beams, and forming a second electrode on the first electrode. In the step of establishing ohmic contact, a surface of the first electrode is irradiated with laser beams such that arithmetic mean roughness of a surface of the second electrode is not greater than 0.2 ?m.
    Type: Application
    Filed: July 8, 2015
    Publication date: February 25, 2016
    Inventors: Hideto TAMASO, Hiroyuki KITABAYASHI, Keiji WADA
  • Silicon carbide semiconductor device and method for manufacturing the same
    Patent number: 9240455
    Abstract: A MOSFET includes an SiC layer including main surfaces. The SiC layer includes an n type drift region, a p type body region, and an n type source region. The MOSFET further includes a gate insulating film formed to be located on a channel region, a gate electrode formed to be located above the channel region, the gate insulating film being sandwiched between said gate electrode and said channel region, and a connection electrode which includes a contact portion having a width smaller than a width of the gate electrode, has electric resistance lower than electric resistance of the gate electrode, and is formed on the gate electrode.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: January 19, 2016
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Keiji Wada
  • SILICON CARBIDE SEMICONDUCTOR DEVICE
    Publication number: 20150380485
    Abstract: The trench has, in a cross-sectional view, a first corner portion which is an intersection between a first sidewall surface and a bottom portion and a second corner portion which is an intersection between a second sidewall surface and the bottom portion. A first layer has a second-conductivity-type region. In a cross-sectional view, the second-conductivity-type region is arranged to intersect with a line which passes through any of the first corner portion and the second corner portion and is in parallel to a <0001> direction of a silicon carbide crystal forming the silicon carbide layer. A ratio calculated by dividing SP by ST is not lower than 20% and not higher than 130%, where ST represents a total area of the trenches in a boundary surface between the first layer and a second layer and SP represents a total area of the second-conductivity-type regions in a plan view.
    Type: Application
    Filed: February 4, 2014
    Publication date: December 31, 2015
    Inventors: Keiji WADA, Yu SAITOH, Takeyoshi MASUDA
  • Silicon carbide semiconductor device and method for manufacturing same
    Patent number: 9224802
    Abstract: Each of first to third impurity regions of a silicon carbide substrate has a portion located on a flat surface of a first main surface. On the flat surface, a gate insulating film connects the first and third impurity regions to each other. On the flat surface, a first main electrode is in contact with the third impurity region. A second main electrode is provided on a second main surface. A side wall insulating film covers a side wall surface of the first main surface. The side wall surface is inclined by not less than 50° and not more than 80° relative to a {000-1} plane. In this way, a leakage current is suppressed in a silicon carbide semiconductor device.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: December 29, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Keiji Wada, Takeyoshi Masuda
  • Silicon carbide semiconductor device
    Patent number: 9224816
    Abstract: A silicon carbide semiconductor device includes a silicon carbide layer, an element region including a semiconductor element portion formed in the silicon carbide layer, a JTE region (first electric field relaxing region), an insulating film disposed on a first main surface and covering the JTE region, and a pad electrode electrically connected to the JTE region. The pad electrode includes an extension portion extending from an end of the JTE region close to the element region in a peripheral direction from the element region toward the JTE region, the extension portion being disposed on the insulating film. The extension portion overlies at least a portion of the JTE region.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: December 29, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Toru Hiyoshi, Masaki Furumai, Mitsuhiko Sakai, Kosuke Uchida
  • Silicon carbide semiconductor device and method for manufacturing same
    Patent number: 9224877
    Abstract: A first main surface of a silicon carbide substrate has a flat surface located in an element portion and a side wall surface located in a termination portion. The silicon carbide substrate has an impurity layer having a portion located at each of the flat surface of the first main surface and a second main surface. On the flat surface, a Schottky electrode is in contact with the impurity layer. On the second main surface, a counter electrode is in contact with the impurity layer. An insulating film covers the side wall surface. The side wall surface is inclined by not less than 50° and not more than 80° relative to a {000-1}plane. This suppresses the leakage current of a silicon carbide semiconductor device.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: December 29, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Keiji Wada
  • SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    Publication number: 20150372128
    Abstract: A silicon carbide film includes a first range having a first breakdown voltage holding layer, a charge compensation region, a first junction terminal region, and a first guard ring region. The silicon carbide film includes a second range having a second breakdown voltage holding layer, a channel forming region, and a source region. The first and second breakdown voltage holding layers constitutes a breakdown voltage holding region having a thickness in an element portion. When voltage is applied to attain a maximum electric field strength of 0.4 MV/cm or more in the breakdown voltage holding region during an OFF state, a maximum electric field strength in the second range within the element portion is configured to be less than ? of a maximum electric field strength in the first range.
    Type: Application
    Filed: December 4, 2013
    Publication date: December 24, 2015
    Inventors: Keiji WADA, Takeyoshi MASUDA, Toru HIYOSHI
  • SILICON CARBIDE SEMICONDUCTOR DEVICE
    Publication number: 20150340443
    Abstract: A silicon carbide semiconductor device includes a silicon carbide layer, an element region including a semiconductor element portion formed in the silicon carbide layer, a JTE region (first electric field relaxing region), an insulating film disposed on a first main surface and covering the JTE region, and a pad electrode electrically connected to the JTE region. The pad electrode includes an extension portion extending from an end of the JTE region close to the element region in a peripheral direction from the element region toward the JTE region, the extension portion being disposed on the insulating film. The extension portion overlies at least a portion of the JTE region.
    Type: Application
    Filed: April 21, 2015
    Publication date: November 26, 2015
    Inventors: Keiji WADA, Toru HIYOSHI, Masaki FURUMAI, Mitsuhiko SAKAI, Kosuke UCHIDA
  • Semiconductor device and method for manufacturing semiconductor device
    Patent number: 9184056
    Abstract: A MOSFET includes a semiconductor substrate having a trench formed in a main surface, a gate oxide film, a gate electrode, and a source interconnection. A semiconductor substrate includes an n-type drift layer and a p-type body layer. The trench is formed to penetrate the body layer and to reach the drift layer. The trench includes an outer peripheral trench arranged to surround an active region when viewed two-dimensionally. On the main surface opposite to the active region when viewed from the outer peripheral trench, a potential fixing region where the body layer is exposed is formed. The source interconnection is arranged to lie over the active region when viewed two-dimensionally. The potential fixing region is electrically connected to the source interconnection.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: November 10, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Keiji Wada, Toru Hiyoshi
  • Method and apparatus for manufacturing silicon carbide semiconductor device
    Patent number: 9184276
    Abstract: A method of manufacturing an SiC semiconductor device includes the steps of forming a first oxide film on a first surface of an SiC semiconductor, removing the first oxide film, and forming a second oxide film constituting the SiC semiconductor device on a second surface exposed as a result of removal of the first oxide film in the SiC semiconductor. Between the step of removing the first oxide film and the step of forming a second oxide film, the SiC semiconductor is arranged in an atmosphere cut off from an ambient atmosphere.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: November 10, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Keiji Wada, Satomi Itoh, Toru Hiyoshi
  • METHOD FOR MANUFACTURING STACKED METAL FOIL, METHOD FOR MANUFACTURING SEALED CELL INCLUDING SAID METHOD, AND SEALED CELL
    Publication number: 20150318535
    Abstract: The method for manufacturing a laminated metal foil (1) according to the present invention includes: a first step of forming, in a weld site (A) of laminated layers of a metal foil (2), by the use of a cutter (C) whose longitudinal cross-sectional shape is a substantially V-shape, a notch (3) that is linear in a planar view and penetrates the laminated layers of the metal foil (2) in a lamination direction (S), to cause the laminated layers of the metal foil (2) to bond to each other along the lamination direction (S) at ends (3a) of a linear notch; and a second step of bringing an electrode (E) for resistance welding into press-contact with the weld site (A) and then energizing the weld site (A) via the electrode (E), to perform resistance welding on the laminated metal foil (1).
    Type: Application
    Filed: July 15, 2015
    Publication date: November 5, 2015
    Applicant: NAG SYSTEM CO., LTD.
    Inventors: Hidemasa NAGAMINE, Keiji WADA
  • Silicon carbide semiconductor device
    Patent number: 9177804
    Abstract: A silicon carbide layer is epitaxially formed on a main surface of a substrate. The silicon carbide layer is provided with a trench having a side wall inclined relative to the main surface. The side wall has an off angle of not less than 50° and not more than 65° relative to a {0001} plane. A gate insulating film is provided on the side wall of the silicon carbide layer. The silicon carbide layer includes: a body region having a first conductivity type and facing a gate electrode with the gate insulating film being interposed therebetween; and a pair of regions separated from each other by the body region and having a second conductivity type. The body region has an impurity density of 5×1016 cm?3 or greater. This allows for an increased degree of freedom in setting a threshold voltage while suppressing decrease of channel mobility.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: November 3, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Toru Hiyoshi, Keiji Wada
  • SILICON CARBIDE SEMICONDUCTOR DEVICE
    Publication number: 20150303266
    Abstract: A silicon carbide semiconductor device has a silicon carbide substrate, a gate insulating film, and a gate electrode. Silicon carbide substrate includes a first impurity region having a first conductivity type, a well region being in contact with the first impurity region and having a second conductivity type which is different from the first conductivity type, and a second impurity region separated from the first impurity region by the well region and having the first conductivity type. The gate insulating film is in contact with the first impurity region and the well region. The gate electrode is in contact with the gate insulating film and is arranged opposite to the well region with respect to the gate insulating film. A specific on-resistance at a voltage which is half a gate driving voltage applied to the gate electrode is smaller than twice the specific on-resistance at the gate driving voltage.
    Type: Application
    Filed: November 6, 2013
    Publication date: October 22, 2015
    Inventors: Toru Hiyoshi, Takeyoshi Masuda, Keiji Wada, Takashi Tsuno
  • SILICON CARBIDE SEMICONDUCTOR DEVICE
    Publication number: 20150303267
    Abstract: First and second ranges of a silicon carbide film have an interface. The first range includes: a first breakdown voltage holding layer having a first conductivity type; and an outer edge embedded region provided at an interface in the outer edge portion and having a second conductivity type. The second range includes a second breakdown voltage holding layer having the first conductivity type. A semiconductor element is formed in the second range. The first range includes: a central section facing the semiconductor element in the central portion in a thickness direction; and an outer edge section facing the semiconductor element in the outer edge portion in the thickness direction. At the interface, the outer edge section includes a portion having an impurity concentration different from the impurity concentration of the central section.
    Type: Application
    Filed: November 27, 2013
    Publication date: October 22, 2015
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi MASUDA, Keiji WADA
  • SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20150295059
    Abstract: A MOSFET includes an SiC layer including main surfaces. The SiC layer includes an a type drift region, a p type body region, and an n type source region. The MOSFET further includes a gate insulating film formed to be located on a channel region, a gate electrode formed to be located above the channel region, the gate insulating film being sandwiched between said gate electrode and said channel region, and a connection electrode which includes a contact portion having a width smaller than a width of the gate electrode, has electric resistance lower than electric resistance of the gate electrode, and is formed on the gate electrode.
    Type: Application
    Filed: March 4, 2015
    Publication date: October 15, 2015
    Inventor: Keiji WADA
  • SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    Publication number: 20150295095
    Abstract: A first main surface of a silicon carbide substrate has a flat surface located in an element portion and a side wall surface located in a termination portion. The silicon carbide substrate has an impurity layer having a portion located at each of the flat surface of the first main surface and a second main surface. On the flat surface, a Schottky electrode is in contact with the impurity layer. On the second main surface, a counter electrode is in contact with the impurity layer. An insulating film covers the side wall surface. The side wall surface is inclined by not less than 50° and not more than 80° relative to a {000-1} plane. This suppresses the leakage current of a silicon carbide semiconductor device.
    Type: Application
    Filed: October 21, 2013
    Publication date: October 15, 2015
    Inventors: Toru Hiyoshi, Keiji Wada
  • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    Publication number: 20150287598
    Abstract: A semiconductor device employing silicon carbide, and the like are provided. In the semiconductor device, even when an electrode material and an upper electrode material are different, a problem does not take place at an interface at which these different types of metals are in contact with each other, thus obtaining high reliability in long-term use. The semiconductor device includes: a contact electrode 16 in contact with silicon carbides 14, 18; and an upper electrode 19 electrically conductive to the contact electrode. The contact electrode 16 is formed of an alloy including titanium, aluminum, and silicon, the upper electrode 19 is formed of aluminum or an aluminum alloy, and the upper electrode achieves the electric conduction to the contact electrode with the upper electrode making contact with the contact electrode.
    Type: Application
    Filed: June 19, 2015
    Publication date: October 8, 2015
    Inventors: Keiji Wada, Hideto Tamaso, Takeyoshi Masuda, Misako Honaga