Patents by Inventor Keiju YAMADA
Keiju YAMADA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9793202Abstract: According to an embodiment, a wireless apparatus includes an interposer substrate, a semiconductor chip, a nonconductive layer, and a conductive film. The interposer substrate includes a conductive portion. The semiconductor chip is mounted on a component mounting face of the interposer substrate. The nonconductive layer is provided on the component mounting face to seal the chip. The conductive film is configured to cover a surface of the nonconductive layer and a side of the interposer substrate and is electrically connected to the conductive portion. The film has a first slot aperture. The conductive portion has a second slot aperture connecting to the first slot aperture. The first and second slot apertures serve as an integrated slot antenna. The antenna has first and second portions. The first portion includes a boundary between the first and second slot apertures and has a width larger than a width of the second portion.Type: GrantFiled: February 22, 2017Date of Patent: October 17, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Koh Hashimoto, Makoto Sano, Keiju Yamada, Makoto Higaki, Akihiko Happoya
-
Patent number: 9721905Abstract: According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer.Type: GrantFiled: May 31, 2016Date of Patent: August 1, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Keiju Yamada, Takashi Yamazaki, Masatoshi Fukuda, Yasuhiro Koshio
-
Publication number: 20170050842Abstract: According to one embodiment, a printed wiring board includes a first magnetic layer, a second magnetic layer, an insulating layer, a first conductor layer, and a second conductor layer. The insulating layer is provided between the first magnetic layer and the second magnetic layer. The first conductor layer is provided between the insulating layer and the first magnetic layer. The second conductor layer is provided between the insulating layer and the second magnetic layer.Type: ApplicationFiled: August 19, 2016Publication date: February 23, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Keiju YAMADA, Kazuo SHIMOKAWA, Tomohiro IGUCHI, Michiko HARA, Motomichi SHIBANO
-
Publication number: 20160276290Abstract: According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer.Type: ApplicationFiled: May 31, 2016Publication date: September 22, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Keiju YAMADA, Takashi YAMAZAKI, Masatoshi FUKUDA, Yasuhiro KOSHIO
-
Patent number: 9401333Abstract: According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.Type: GrantFiled: July 16, 2015Date of Patent: July 26, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Keiju Yamada, Masaaki Ishida
-
Patent number: 9362196Abstract: According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer.Type: GrantFiled: July 13, 2011Date of Patent: June 7, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Keiju Yamada, Takashi Yamazaki, Masatoshi Fukuda, Yasuhiro Koshio
-
Publication number: 20160091575Abstract: A magnetic shielded package includes a magnetic device, a first magnetic shield member, and a second magnetic shield member. The first magnetic shield member is disposed below the magnetic device. The second magnetic shield member is disposed on the first magnetic shield member so as to cover the magnetic device. An opening portion is formed in the first magnetic shield member (i) at such a position as not to be adjacent to an outer circumference of the first magnetic shield member or (ii) an upper wall of the second magnetic shield member.Type: ApplicationFiled: September 30, 2015Publication date: March 31, 2016Inventors: Keiju YAMADA, Mikiya llDA, Kei MASUNISHI, Kazuo SHIMOKAWA, Hideaki FUKUZAWA, Michiko HARA
-
Publication number: 20150325530Abstract: According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.Type: ApplicationFiled: July 16, 2015Publication date: November 12, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Keiju YAMADA, Masaaki Ishida
-
Publication number: 20150279791Abstract: According to one embodiment, a semiconductor device includes a part or entirety of a switching power supply, at least one semiconductor element, and at least one line composed of a inner conductor and a soft magnetic member sheathing the inner conductor. The semiconductor device further includes, for example, a circuit substrate on which the part or entirety of the switching power supply and the semiconductor elements are mounted. The lines are mounted on the circuit substrate.Type: ApplicationFiled: February 10, 2015Publication date: October 1, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Keiju YAMADA
-
Patent number: 9123731Abstract: According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.Type: GrantFiled: November 25, 2014Date of Patent: September 1, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Keiju Yamada, Masaaki Ishida
-
Publication number: 20150076671Abstract: According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.Type: ApplicationFiled: November 25, 2014Publication date: March 19, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Keiju Yamada, Masaaki Ishida
-
Patent number: 8952505Abstract: According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.Type: GrantFiled: June 3, 2014Date of Patent: February 10, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Keiju Yamada, Masaaki Ishida
-
Patent number: 8874048Abstract: According to one embodiment, a wireless device includes a board, a semiconductor chip, a radiation element, a sealing resin, a conductive layer, and a first conductive wall. The semiconductor chip is mounted on the board and includes a transmission/reception circuit. The radiation element is formed on the board. The sealing resin seals the semiconductor chip. The conductive layer covers at least a portion of a surface of the sealing resin. The first conductive wall is provided between the semiconductor chip and the radiation element and is connected to the conductive layer.Type: GrantFiled: September 5, 2012Date of Patent: October 28, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yukako Tsutsumi, Koh Hashimoto, Takayoshi Ito, Koji Akita, Keiju Yamada
-
Patent number: 8860190Abstract: According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.Type: GrantFiled: January 25, 2012Date of Patent: October 14, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Keiju Yamada, Masaaki Ishida
-
Publication number: 20140284776Abstract: According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.Type: ApplicationFiled: June 3, 2014Publication date: September 25, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Keiju YAMADA, Masaaki Ishida
-
Publication number: 20140266532Abstract: According to one embodiment, a line is provided. The line includes a center conductor and a covering portion. The covering portion covers the center conductor. The covering portion includes at least one layer that is made of a soft magnetic material and is thinner than a skin depth at a frequency where supply of a signal or power is performed.Type: ApplicationFiled: September 27, 2013Publication date: September 18, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Keiju YAMADA
-
Publication number: 20130222401Abstract: According to the embodiments, a semiconductor package includes a semiconductor chip, a first conductive layer, a second conductive layer, and a power feeder. The semiconductor chip is provided on a substrate, is sealed with a resin, and contains a transmission/reception circuit. The first conductive layer is grounded and covers a first region on a surface of the resin. The second conductive layer is not grounded and covers a second region on the surface of the resin other than the first region. A power feeder electrically connects the semiconductor chip to the second conductive layer.Type: ApplicationFiled: August 31, 2012Publication date: August 29, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takayoshi ITO, Koh HASHIMOTO, Yukako TSUTSUMI, Koji AKITA, Keiju YAMADA
-
Publication number: 20130222196Abstract: According to one embodiment, a wireless device includes a circuit board, a semiconductor chip, a sealing resin, a conductive film, and an antenna element. The semiconductor chip includes a transmitting/receiving circuit and is mounted on the circuit board. The sealing resin seals the semiconductor chip. The conductive film covers a first surface portion of the sealing resin. An aperture is formed in a portion of the conductive film that corresponds to a second surface portion of the sealing resin other than the first surface portion, and the second surface portion is included in a side surface of the sealing resin and closest to an antenna terminal connected to the antenna element.Type: ApplicationFiled: September 5, 2012Publication date: August 29, 2013Applicant: Kabushiki Kaisha TOSHIBAInventors: Koh HASHIMOTO, Yukako Tsutsumi, Takayoshi Ito, Koji Akita, Keiju Yamada
-
Publication number: 20130225102Abstract: According to one embodiment, a wireless device includes a board, a semiconductor chip, a radiation element, a sealing resin, a conductive layer, and a first conductive wall. The semiconductor chip is mounted on the board and includes a transmission/reception circuit. The radiation element is formed on the board. The sealing resin seals the semiconductor chip. The conductive layer covers at least a portion of a surface of the sealing resin. The first conductive wall is provided between the semiconductor chip and the radiation element and is connected to the conductive layer.Type: ApplicationFiled: September 5, 2012Publication date: August 29, 2013Applicant: Kabushiki Kaisha TOSHIBAInventors: Yukako TSUTSUMI, Koh HASHIMOTO, Takayoshi ITO, Koji AKITA, Keiju YAMADA
-
Publication number: 20120193770Abstract: According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.Type: ApplicationFiled: January 25, 2012Publication date: August 2, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Keiju YAMADA, Masaaki Ishida