Patents by Inventor Keishi Takaki

Keishi Takaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180375279
    Abstract: An optical module comprising a first optical fiber corresponding to an incidence side for laser light a second optical fiber corresponding to an emission side for the laser light; and a connection protecting portion that is provided and located so as to cover a connection site for optically connecting the first optical fiber and the second optical fiber, wherein the second optical fiber has a larger core diameter than the first optical fiber, the connection site is a site where a core portion of the first optical fiber and a core portion of the second optical fiber are connected to each other in a discontinuous shape, and the connection protecting portion is formed of a thermally conductive protective material and/or a photorefractive protective material includes refractive index that is equal to or higher than that of a clad portion of the first optical fiber.
    Type: Application
    Filed: August 3, 2018
    Publication date: December 27, 2018
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Koji KAJIWARA, Keishi TAKAKI
  • Patent number: 9911842
    Abstract: A nitride semiconductor device includes; a semiconductor stack configured with a plurality of semiconductor layers made of nitride semiconductors provided on a base having a conductive portion; a first electrode provided on a portion of a semiconductor layer of the semiconductor layers configuring the semiconductor stack; a second electrode provided on a portion of a semiconductor layer of the semiconductor layers configuring the semiconductor stack separately from the first electrode; a first wiring provided at an upper layer of the first electrode; and a second wiring provided at an upper layer of the second electrode. A low permittivity area being a portion of which permittivity is lower than permittivities of the nitride semiconductors configuring the semiconductor stack at a lower layer of a portion of at least one of the first electrode and the second electrode other than a portion being junctioned with the semiconductor stack electrically.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: March 6, 2018
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Kazuyuki Umeno, Shinya Otomo, Keishi Takaki, Jiang Li, Takuya Kokawa, Ryosuke Tamura, Masayuki Iwami, Shusuke Kaya, Hirotatsu Ishii
  • Patent number: 9653589
    Abstract: A semiconductor multi-layer substrate includes a substrate made of Si and a multi-layer semiconductor layer. The multi-layer semiconductor layer includes an active layer made of a nitride semiconductor, a first warp control layer being formed between the substrate and the active layer and giving a predetermined warp to the substrate, and a second warp control layer made of a nitride semiconductor of which amount of an increase in a warp per a unit thickness is smaller than an amount of increase in the warp per a unit thickness of the first warp control layer. A total thickness of the multi-layer semiconductor layer is equal to or larger than 4 ?m.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: May 16, 2017
    Assignees: FURUKAWA ELECTRIC CO., LTD., FUJI ELECTRIC CO., LTD.
    Inventors: Kazuyuki Umeno, Tatsuyuki Shinagawa, Keishi Takaki, Ryosuke Tamura, Shinya Ootomo
  • Publication number: 20160225889
    Abstract: A nitride semiconductor device includes; a semiconductor stack configured with a plurality of semiconductor layers made of nitride semiconductors provided on a base having a conductive portion; a first electrode provided on a portion of a semiconductor layer of the semiconductor layers configuring the semiconductor stack; a second electrode provided on a portion of a semiconductor layer of the semiconductor layers configuring the semiconductor stack separately from the first electrode; a first wiring provided at an upper layer of the first electrode; and a second wiring provided at an upper layer of the second electrode. A low permittivity area being a portion of which permittivity is lower than permittivities of the nitride semiconductors configuring the semiconductor stack at a lower layer of a portion of at least one of the first electrode and the second electrode other than a portion being junctioned with the semiconductor stack electrically.
    Type: Application
    Filed: April 13, 2016
    Publication date: August 4, 2016
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Kazuyuki UMENO, Shinya Otomo, Keishi Takaki, Jiang Li, Takuya Kokawa, Ryosuke Tamura, Masayuki Iwami, Shusuke Kaya, Hirotatsu Ishii
  • Patent number: 9300114
    Abstract: Provided is a laser device comprising a substrate, an active layer, and a current confinement layer. The current confinement layer includes an oxide layer that is formed extending from a edge of the current confinement layer in a parallel plane parallel to a surface of the substrate, toward a center of the current confinement layer along the parallel plane, and that does not have an inflection point between the edge and a tip portion formed closer to the center or has a plurality of inflection points formed between the edge and the tip portion.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: March 29, 2016
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Hitoshi Shimizu, Toshihito Suzuki, Yasumasa Kawakita, Keishi Takaki
  • Patent number: 9276066
    Abstract: A semiconductor multi-layer substrate includes a substrate, a buffer layer formed on the substrate and made of a nitride semiconductor, an electric-field control layer formed on the buffer layer and made of a nitride semiconductor, the electric-field control layer having conductivity in the substrate's lateral direction, an electric-field relaxation layer formed on the electric-field control layer and made of a nitride semiconductor, and an active layer formed on the electric-field relaxation layer and made of an nitride semiconductor. A resistance in the substrate's lateral direction of the electric-field control layer is equal to or smaller than 10 times a resistance of the electric-field relaxation layer, and a ratio of an electric field share between the electric-field relaxation layer and the buffer layer is controlled by a ratio between a thickness of the electric-field relaxation layer and a thickness of the buffer layer.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: March 1, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryosuke Tamura, Kazuyuki Umeno, Tatsuyuki Shinagawa, Keishi Takaki, Ryohei Makino, Jiang Li
  • Publication number: 20150221725
    Abstract: A semiconductor multi-layer substrate includes a substrate, a buffer layer formed on the substrate and made of a nitride semiconductor, an electric-field control layer formed on the buffer layer and made of a nitride semiconductor, the electric-field control layer having conductivity in the substrate's lateral direction, an electric-field relaxation layer formed on the electric-field control layer and made of a nitride semiconductor, and an active layer formed on the electric-field relaxation layer and made of an nitride semiconductor. A resistance in the substrate's lateral direction of the electric-field control layer is equal to or smaller than 10 times a resistance of the electric-field relaxation layer, and a ratio of an electric field share between the electric-field relaxation layer and the buffer layer is controlled by a ratio between a thickness of the electric-field relaxation layer and a thickness of the buffer layer.
    Type: Application
    Filed: July 5, 2013
    Publication date: August 6, 2015
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Ryosuke Tamura, Kazuyuki Umeno, Tatsuyuki Shinagawa, Keishi Takaki, Ryohei Makino, Jiang Li
  • Publication number: 20150069410
    Abstract: A semiconductor device includes: a base; an electron transit layer layered on the base; an electron-supplying layer being configured by layering a plurality of AlN layers and GaN layers alternately on the electron transit layer and having an average Al composition x; an etching sacrificial layer layered on the electron-supplying layer and made of AlyGa1-yN (0<y<1) having an Al composition y; a field plate layer layered on the etching sacrificial layer and made of AlzGa1-zN (0?z<1, z<y) having an Al composition z; and an electrode connected to the etching sacrificial layer and being provided in an area in which a part of the field plate layer is removed until reaching the etching sacrificial layer.
    Type: Application
    Filed: November 19, 2014
    Publication date: March 12, 2015
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Kazuyuki UMENO, Hiroshi Kambayashi, Keishi Takaki
  • Patent number: 8941149
    Abstract: A semiconductor device includes: a first semiconductor layer formed on a substrate and formed of a nitride-based semiconductor; a second semiconductor layer formed on a surface of the first semiconductor layer and formed of a nitride-based semiconductor having a wider band-gap than the first semiconductor layer; first and second electrodes formed on a surface of the second semiconductor layer; an inter-electrode insulator film that is formed between the first and second electrodes on the surface of the second semiconductor layer; and a dielectric constant adjustment layer formed on the inter-electrode insulator film and formed of an electric insulator. The first electrode has a field plate portion formed so as to ride on the inter-electrode insulator film, and the dielectric constant adjustment layer has a first layer that contacts a lateral end portion of the field plate portion and a second layer formed on the first layer.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: January 27, 2015
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Jiang Li, Keishi Takaki, Ryosuke Tamura, Yoshihiro Ikura
  • Publication number: 20140374771
    Abstract: A semiconductor multi-layer substrate includes a substrate made of Si and a multi-layer semiconductor layer. The multi-layer semiconductor layer includes an active layer made of a nitride semiconductor, a first warp control layer being formed between the substrate and the active layer and giving a predetermined warp to the substrate, and a second warp control layer made of a nitride semiconductor of which amount of an increase in a warp per a unit thickness is smaller than an amount of increase in the warp per a unit thickness of the first warp control layer. A total thickness of the multi-layer semiconductor layer is equal to or larger than 4 ?m.
    Type: Application
    Filed: September 10, 2014
    Publication date: December 25, 2014
    Applicants: Furukawa Electric Co., Ltd., Fuji Electric Co., Ltd.
    Inventors: Kazuyuki UMENO, Tatsuyuki Shinagawa, Keishi Takaki, Ryosuke Tamura, Shinya Ootomo
  • Patent number: 8861562
    Abstract: Provided is a vertical light emitting device comprising an upper multilayer reflective film and a lower multilayer reflective film that are formed facing each other and oscillate light; an intermediate layer that is formed below the upper multilayer reflective film and includes a layer having a different composition than the upper multilayer reflective film; and an electrode portion that is formed to sandwich the intermediate layer in a cross-sectional plane parallel to an oscillation direction of the light and to have a top end that is higher than a top surface of the intermediate layer. After the electrode portion is formed to sandwich the intermediate layer, the upper multilayer reflective film is layered on the intermediate layer.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: October 14, 2014
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Toshihito Suzuki, Keishi Takaki, Suguru Imai, Yasumasa Kawakita
  • Publication number: 20140284660
    Abstract: A method for manufacturing a semiconductor wafer includes the steps of forming, on a first principal surface of a substrate, a compound semiconductor layer different in kind from the substrate, and removing, by etching, a part of the compound semiconductor layer. The part of the compound semiconductor layer is formed on an outer peripheral portion of the first principal surface of the substrate.
    Type: Application
    Filed: July 10, 2013
    Publication date: September 25, 2014
    Inventors: Ryohei MAKINO, Takao KUMADA, Masaharu EDO, Keishi TAKAKI
  • Publication number: 20140117410
    Abstract: A semiconductor device includes: a first semiconductor layer formed on a substrate and formed of a nitride-based semiconductor; a second semiconductor layer formed on a surface of the first semiconductor layer and formed of a nitride-based semiconductor having a wider band-gap than the first semiconductor layer; first and second electrodes formed on a surface of the second semiconductor layer; an inter-electrode insulator film that is formed between the first and second electrodes on the surface of the second semiconductor layer; and a dielectric constant adjustment layer formed on the inter-electrode insulator film and formed of an electric insulator. The first electrode has a field plate portion formed so as to ride on the inter-electrode insulator film, and the dielectric constant adjustment layer has a first layer that contacts a lateral end portion of the field plate portion and a second layer formed on the first layer.
    Type: Application
    Filed: July 10, 2013
    Publication date: May 1, 2014
    Inventors: Jiang LI, Keishi Takaki, Ryosuke Tamura, Yoshihiro Ikura
  • Patent number: 8532155
    Abstract: There is provided an optical interconnection system including a plurality of semiconductor integrated devices each including a surface emitting laser array device including a plurality of surface emitting laser devices each emitting an output laser signal light of a different wavelength modulated based on an input modulated signal, a silicon optical waveguide that guides output laser signal lights emitted from the surface emitting laser devices of each of the semiconductor integrated devices to another semiconductor integrated device, a plurality of optical couplers respectively corresponding to the semiconductor integrated devices and guiding the output laser signal lights to the silicon optical waveguide, and a plurality of optical splitters respectively corresponding to the semiconductor integrated devices, receiving the output laser signal lights guided by the silicon optical waveguide, and inputting an input laser signal light to a corresponding one of the semiconductor integrated devices.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: September 10, 2013
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Keishi Takaki, Masaki Funabashi, Yasumasa Kawakita, Naoki Tsukiji
  • Patent number: 8494022
    Abstract: A surface emitting laser is formed of a composition in which bandgap energy of layers from immediately above a current confinement layer to a second conductivity type contact layer is reduced towards the second conductivity type contact layer in a stacking direction, and a composition in which bandgap energy of layers from immediately below the current confinement layer to a first conductivity type contact layer is reduced towards the first conductivity type contact layer in a stacking direction while bypassing a quantum well layer or a quantum dot of an active layer, and includes a second conductivity type cladding layer including a material for reducing the mobility of carriers.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: July 23, 2013
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Hitoshi Shimizu, Takeo Kageyama, Keishi Takaki, Norihiro Iwai
  • Patent number: 8488644
    Abstract: A semiconductor laser element includes a first electrode, a second electrode, a first reflecting mirror, a second reflecting mirror, and a resonator. The resonator includes an active layer, a current confinement layer, a first semiconductor layer having a first doping concentration formed at a side opposite to the active layer across the current confinement layer, and a second semiconductor layer having a second doping concentration higher than the first doping concentration formed between the first semiconductor layer and the current confinement layer. The first electrode is provided to contact a part of a surface of the first semiconductor layer. The first semiconductor layer has a diffusion portion into which a component of the first electrode diffuses. The second semiconductor layer contacts the diffusion portion. The second semiconductor layer is positioned at a node of a standing wave at a time of laser oscillation of the semiconductor laser element.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: July 16, 2013
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Suguru Imai, Keishi Takaki, Norihiro Iwai, Kinuka Tanabe, Hitoshi Shimizu, Hirotatsu Ishii
  • Publication number: 20130010822
    Abstract: Provided is a vertical light emitting device comprising an upper multilayer reflective film and a lower multilayer reflective film that are formed facing each other and oscillate light; an intermediate layer that is formed below the upper multilayer reflective film and includes a layer having a different composition than the upper multilayer reflective film; and an electrode portion that is formed to sandwich the intermediate layer in a cross-sectional plane parallel to an oscillation direction of the light and to have a top end that is higher than a top surface of the intermediate layer. After the electrode portion is formed to sandwich the intermediate layer, the upper multilayer reflective film is layered on the intermediate layer.
    Type: Application
    Filed: June 22, 2012
    Publication date: January 10, 2013
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Toshihito SUZUKI, Keishi TAKAKI, Suguru IMAI, Yasumasa KAWAKITA
  • Publication number: 20120320447
    Abstract: There is provided a semiconductor laser that includes a dielectric multilayer mirror (116) with a structure including high-refractive-index dielectric layers and low-refractive-index dielectric layers arranged periodically, and a cavity (110) that includes the dielectric multilayer mirror (116), on at least one facet thereof, and an active layer (105). A non-linear layer that is non-linear with respect to primary mode laser light is formed in at least one layer of either the high-refractive-index dielectric layers or the low-refractive-index dielectric layers.
    Type: Application
    Filed: December 20, 2011
    Publication date: December 20, 2012
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Keishi TAKAKI, Hirotatsu ISHII, Norihiro IWAI, Shinya OOTOMO
  • Patent number: 8306080
    Abstract: A surface emitting laser apparatus includes an arithmetic processing unit including an I/O unit for externally inputting an instruction and a core unit that performs an operation based on the instruction and outputs a differential voltage signal modulated with a predetermined amplitude according to a result of the operation, capacitors respectively arranged on output paths of the differential voltage signal, and a surface emitting laser device that is directly connected to the arithmetic processing unit via the capacitors. An I/O voltage and a core voltage are externally supplied to the I/O unit and the core unit, respectively. The arithmetic processing unit generates a driving voltage signal by superimposing the differential voltage signal with the core voltage commonly supplied as a bias voltage without stepping up or down the core voltage and without amplifying the differential voltage signal and supplies the driving voltage signal to the surface emitting laser device.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: November 6, 2012
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Keishi Takaki, Naoki Tsukiji, Suguru Imai
  • Publication number: 20120251039
    Abstract: Provided is a laser device comprising a substrate, an active layer, and a current confinement layer. The current confinement layer includes an oxide layer that is formed extending from a edge of the current confinement layer in a parallel plane parallel to a surface of the substrate, toward a center of the current confinement layer along the parallel plane, and that does not have an inflection point between the edge and a tip portion formed closer to the center or has a plurality of inflection points formed between the edge and the tip portion.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 4, 2012
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Hitoshi SHIMIZU, Toshihito SUZUKI, Yasumasa KAWAKITA, Keishi TAKAKI