Patents by Inventor Keisuke Kimura
Keisuke Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150249459Abstract: To compensate for non-linearity of an AD conversion unit and non-linearity of a DA conversion unit in an electronic system including the DA conversion unit and the AD conversion unit, an electronic system includes an A/D conversion unit, a D/A conversion unit, an AD conversion compensation unit, a DA conversion compensation unit, and a calibration unit. During a calibration operation period, the calibration unit sets an operating characteristic of the AD conversion compensation unit and an operating characteristic of the DA conversion compensation unit. The operating characteristic of the AD conversion compensation unit set during the calibration operation period compensates for non-linearity of AD conversion of the A/D conversion unit. The operating characteristic of the DA conversion compensation unit set during the calibration operation period compensates for non-linearity of DA conversion of the D/A conversion unit.Type: ApplicationFiled: May 13, 2015Publication date: September 3, 2015Inventors: Takashi OSHIMA, Tatsuji MATSUURA, Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO, Keisuke KIMURA
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Patent number: 9124284Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.Type: GrantFiled: December 22, 2014Date of Patent: September 1, 2015Assignee: Renesas Electronics CorporationInventors: Keisuke Kimura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto
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Publication number: 20150229322Abstract: A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential signal is passive-amplified twice before carrying out a successive approximation type analog-digital conversion operation. The passive amplification is attained by providing a plurality of capacitances which carry out a sampling operation, and switching these connection relation by using switches. Without being accompanied by the increase of the consumed power and the chip size, an influence by the noise of s comparator is reduced to a half so that the effective resolution can be increased for one bit.Type: ApplicationFiled: April 21, 2015Publication date: August 13, 2015Inventors: Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO, Keisuke KIMURA, Takashi OSHIMA, Tatsuji MATSUURA
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Patent number: 9100034Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.Type: GrantFiled: March 10, 2014Date of Patent: August 4, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Oshima, Tatsuji Matsuura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto, Keisuke Kimura
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Publication number: 20150188555Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.Type: ApplicationFiled: December 22, 2014Publication date: July 2, 2015Inventors: Keisuke KIMURA, Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO
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Publication number: 20150171879Abstract: A semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted.Type: ApplicationFiled: September 16, 2014Publication date: June 18, 2015Inventors: Keisuke KIMURA, Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO
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Patent number: 9054726Abstract: A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential signal is passive-amplified twice before carrying out a successive approximation type analog-digital conversion operation. The passive amplification is attained by providing a plurality of capacitances which carry out a sampling operation, and switching these connection relation by using switches. Without being accompanied by the increase of the consumed power and the chip size, an influence by the noise of s comparator is reduced to a half so that the effective resolution can be increased for one bit.Type: GrantFiled: January 21, 2014Date of Patent: June 9, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuichi Okuda, Hideo Nakane, Takaya Yamamoto, Keisuke Kimura, Takashi Oshima, Tatsuji Matsuura
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Patent number: 9054723Abstract: To compensate for non-linearity of an AD conversion unit and non-linearity of a DA conversion unit in an electronic system including the DA conversion unit and the AD conversion unit, an electronic system includes an A/D conversion unit, a D/A conversion unit, an AD conversion compensation unit, a DA conversion compensation unit, and a calibration unit. During a calibration operation period, the calibration unit sets an operating characteristic of the AD conversion compensation unit and an operating characteristic of the DA conversion compensation unit. The operating characteristic of the AD conversion compensation unit set during the calibration operation period compensates for non-linearity of AD conversion of the A/D conversion unit. The operating characteristic of the DA conversion compensation unit set during the calibration operation period compensates for non-linearity of DA conversion of the D/A conversion unit.Type: GrantFiled: May 12, 2014Date of Patent: June 9, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Oshima, Tatsuji Matsuura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto, Keisuke Kimura
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Patent number: 9041053Abstract: When a semiconductor substrate of a semiconductor device is viewed from above, an isolation region, an IGBT region, and a diode region are all formed adjacent to each other. A deep region that is connected to a body region and an anode region is formed in the isolation region. A drift region is formed extending across the isolation region, the IGBT region, and the diode region, inside the semiconductor substrate. A collector region that extends across the isolation region, the IGBT region and the diode region, and a cathode region positioned in the diode region, are formed in a region exposed on a lower surface of the semiconductor substrate. A boundary between the collector region and the cathode region is in the diode region, in a cross-section that cuts across a boundary between the isolation region and the diode region, and divides the isolation region and the diode region.Type: GrantFiled: January 23, 2013Date of Patent: May 26, 2015Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Keisuke Kimura, Satoru Kameyama, Masaki Koyama, Sachiko Aoi
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Patent number: 9007245Abstract: A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.Type: GrantFiled: July 29, 2014Date of Patent: April 14, 2015Assignee: Renesas Electronics CorporationInventors: Keisuke Kimura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto, Tatsuji Matsuura
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Patent number: 8941889Abstract: An overhead image reading apparatus 1 includes: an image-capturing unit 22 that captures an image of a medium S to be read from above when the medium S to be read is placed on a placement surface 2; a light source 21 that irradiates the medium S to be read with light when the image-capturing unit 22 captures the image of the medium S to be read; and a light blocking portion 25 that blocks light above an upper-end position of light emitted from the light source 21. As a result, the user 100 can be prevented from seeing light from the light source 21 with his/her eyes and from being dazzled with an unpleasant feeling by light from the light source 21 during reading on the medium S to be read.Type: GrantFiled: April 11, 2013Date of Patent: January 27, 2015Assignee: PFU LimitedInventor: Keisuke Kimura
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Publication number: 20140361333Abstract: When a semiconductor substrate of a semiconductor device is viewed from above, an isolation region, an IGBT region, and a diode region are all formed adjacent to each other. A deep region that is connected to a body region and an anode region is formed in the isolation region. A drift region is formed extending across the isolation region, the IGBT region, and the diode region, inside the semiconductor substrate. A collector region that extends across the isolation region, the IGBT region and the diode region, and a cathode region positioned in the diode region, are formed in a region exposed on a lower surface of the semiconductor substrate. A boundary between the collector region and the cathode region is in the diode region, in a cross-section that cuts across a boundary between the isolation region and the diode region, and divides the isolation region and the diode region.Type: ApplicationFiled: January 23, 2013Publication date: December 11, 2014Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Keisuke Kimura, Satoru Kameyama, Masaki Koyama, Sachiko Aoi
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Publication number: 20140354867Abstract: A linear light source apparatus is provided, being configured to convert light emitted from one light emitting element to light extended linearly, and output thus converted light. There is a lens that diffuses light flux within a predetermined region including the optical axis of the light emitting element, out of the light incident from the light emitting element, at a predetermined diffusion angle in the second direction (x-direction). The light is made to converge with respect to the first direction (y-direction). This converts the light from one light emitting element to light extended linearly and outputs the converted light. As for the second direction (x-direction), it is possible to make the light flux sparse in the predetermined region, and in the region outside thereof, the light flux is rendered to be dense.Type: ApplicationFiled: June 4, 2014Publication date: December 4, 2014Applicants: Stanley Electric Co., Ltd., PFU LIMITEDInventors: Yosuke Mizuki, Keisuke Kimura, Masanari Takabatake, Sousuke Aono
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Publication number: 20140333459Abstract: To compensate for non-linearity of an AD conversion unit and non-linearity of a DA conversion unit in an electronic system including the DA conversion unit and the AD conversion unit, an electronic system includes an A/D conversion unit, a D/A conversion unit, an AD conversion compensation unit, a DA conversion compensation unit, and a calibration unit. During a calibration operation period, the calibration unit sets an operating characteristic of the AD conversion compensation unit and an operating characteristic of the DA conversion compensation unit. The operating characteristic of the AD conversion compensation unit set during the calibration operation period compensates for non-linearity of AD conversion of the A/D conversion unit. The operating characteristic of the DA conversion compensation unit set during the calibration operation period compensates for non-linearity of DA conversion of the D/A conversion unit.Type: ApplicationFiled: May 12, 2014Publication date: November 13, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takashi OSHIMA, Tatsuji MATSUURA, Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO, Keisuke KIMURA
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Publication number: 20140333461Abstract: A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.Type: ApplicationFiled: July 29, 2014Publication date: November 13, 2014Inventors: Keisuke Kimura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto, Tatsuji Matsuura
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Patent number: 8883885Abstract: Disclosed is a polyamide resin composition comprising 0.01 to 50 parts by mass of cellulose fiber having an average fiber diameter of 10 ?m or less in relation to 100 parts by mass of a polyamide resin. Also disclosed is a method for producing the polyamide resin composition, wherein the monomer constituting the polyamide resin is subjected to a polymerization reaction in the presence of the cellulose fiber having an average fiber diameter of 10 ?m or less in a water-containing state.Type: GrantFiled: April 6, 2011Date of Patent: November 11, 2014Assignee: Unitika Ltd.Inventors: Miho Nakai, Keisuke Kimura
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Patent number: 8886141Abstract: Provided is a semiconductor device that is capable of performing background calibration during a reception operation without adversely affecting reception characteristics. During a reception operation, the semiconductor device detects a timing at which an invalid received signal occurs upon a gain change or a reception channel change and performs background calibration at the detected timing. In this instance, as the received signal is invalid, performing the calibration does not further decrease the substantial accuracy of reception. Moreover, an unnecessary signal component, which would arise when the background calibration is performed at fixed intervals, will not be generated as far as the background calibration is performed at random timing.Type: GrantFiled: October 22, 2012Date of Patent: November 11, 2014Assignee: Renesas Electronics CorporationInventors: Hideo Nakane, Keisuke Kimura, Takaya Yamamoto, Tatsuji Matsuura, Ryuichi Ujiie
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Patent number: 8854700Abstract: An image reading apparatus includes a main body, a rotation unit supported on the main body so as to be rotatable around a rotation axis, an imaging unit that is mounted on the rotation unit at an outward position in a radial direction of the rotation axis and images a medium to be read that is placed on a placement surface located under the rotation unit in the vertical direction, and a light source that irradiates the medium to be read with light. The light source and the imaging unit can be arranged with a relative positional relationship capable of suppressing specular reflected light of light that is emitted from the light source and reflected by the medium to be read from being incident on the imaging unit.Type: GrantFiled: February 8, 2012Date of Patent: October 7, 2014Assignee: PFU LimitedInventor: Keisuke Kimura
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Publication number: 20140253352Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.Type: ApplicationFiled: March 10, 2014Publication date: September 11, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takashi OSHIMA, Tatsuji MATSUURA, Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO, Keisuke KIMURA
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Patent number: 8823565Abstract: A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.Type: GrantFiled: July 12, 2013Date of Patent: September 2, 2014Assignee: Renesas Electronics CorporationInventors: Keisuke Kimura, Tatsuji Matsuura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto