Patents by Inventor Keisuke Kobayashi

Keisuke Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162297
    Abstract: A silicon carbide semiconductor device includes: a trench formed on an upper surface of a silicon carbide semiconductor substrate; a gate electrode in the trench; an n-type drift layer, a p-type guard region, an n-type semiconductor region to which a source potential is applied, a p-type body layer and an n-type current diffusion region that have a lower impurity concentration than that of the guard region, the n-type drift layer, the p-type guard region, the n-type semiconductor region, the p-type body layer, and the n-type current diffusion region being formed in the silicon carbide semiconductor substrate; and an n-type JFET region that is formed in the silicon carbide semiconductor substrate so as to be separated from the trench and that connects the current diffusion region and the drift layer. The semiconductor region is separated from the drift layer, the current diffusion region, and the JFET region.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 16, 2024
    Applicant: Hitachi, Ltd.
    Inventors: Takeru SUTO, Keisuke KOBAYASHI, Tomoka SUEMATSU, Haruka SHIMIZU
  • Publication number: 20240072132
    Abstract: A semiconductor device includes: an insulated gate electrode structure provided in a semiconductor substrate; a base region; a first main electrode region; a contact plug buried in a trench penetrating the first main electrode region to reach the base region with a barrier metal film interposed; an interlayer insulating film provided with a contact hole integrally connected to the trench; a contact region provided in contact with a bottom of the trench; and a second main electrode region, wherein an opening width at a lower end of the contact hole conforms to a width at an opening of the trench, an upper part of a side wall continued from the opening of the trench has a curved surface convex to an outside, and a lower part of the side wall continuously connected to the bottom of the trench has a curved surface convex to the outside.
    Type: Application
    Filed: July 25, 2023
    Publication date: February 29, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Keisuke KOBAYASHI, Makoto ENDOU, Shiomi INOUE
  • Publication number: 20230308598
    Abstract: An image processing device includes an angle detection unit configured to detect an angle between a front portion of a movable apparatus and a rear portion of the movable apparatus, a combining unit configured to combine an image captured by a front portion imaging unit provided at the front portion and an image captured by a rear portion imaging unit provided at the rear portion, and a boundary calculation unit configured to calculate a boundary between the images combined in the combining unit on the basis of the angle.
    Type: Application
    Filed: March 9, 2023
    Publication date: September 28, 2023
    Inventors: TERUYUKI HIGASHIYAMA, IKUNARI NAKAHARA, KEISUKE KOBAYASHI
  • Publication number: 20220376109
    Abstract: To provide a technique capable of improving performance and reliability of a semiconductor device. An n?-type epitaxial layer (12) is formed on an n-type semiconductor substrate (11), and a p+-type body region (14), n+-type current spreading regions (16, 17), and a trench. TR are formed in the n?-type epitaxial layer (12). A bottom surface B1 of the trench TR is located in the p+-type body region (14), a side surface S1 of the trench TR is in contact with the n+-type current spreading region (17), and a side surface S2 of the trench TR is in contact with the n+-type current spreading region (16). Here, a ratio of silicon is higher than a ratio of carbon in an upper surface T1 of the n?-type epitaxial layer (12), and the bottom surface B1, the side surface S1, and the side surface 32 of the trench.
    Type: Application
    Filed: June 18, 2020
    Publication date: November 24, 2022
    Inventors: Keisuke Kobayashi, Kumiko Konishi, Akio Shima, Norihito Yabuki, Yusuke Sudoh, Satoru Nogami, Makoto Kitabatake
  • Publication number: 20220291155
    Abstract: [Problem] The present invention aims to solve the problems that size of X-ray monochromater crystal assembly is restricted and the vacuum of the X-ray source and the vacuum of the analysis chamber cannot be separated.
    Type: Application
    Filed: April 28, 2022
    Publication date: September 15, 2022
    Inventors: Keisuke Kobayashi, Yoshiko Kobayashi
  • Publication number: 20210280677
    Abstract: A SiC wafer including a SiC substrate and an epitaxial layer formed on the SiC substrate and containing SiC is provided, and a composition ratio of C—Si of an upper surface of the epitaxial layer is 50 atm % or less.
    Type: Application
    Filed: February 24, 2021
    Publication date: September 9, 2021
    Applicant: HITACHI METALS, LTD.
    Inventors: Keisuke KOBAYASHI, Akio SHIMA
  • Patent number: 11031238
    Abstract: In a silicon carbide stacked substrate, the efficiency of converting the basal plane dislocation (BPD) which is a fault to deteriorate the current-carrying reliability into a threading edge dislocation (TED) which is a harmless fault is improved, thereby improving the reliability of the silicon carbide stacked substrate. As means therefor, in a silicon carbide stacked substrate including a SiC substrate and a buffer layer and a drift layer which are epitaxial layers sequentially formed on the SiC substrate, a semiconductor layer having an impurity concentration lower than those of the SiC substrate and the buffer layer and higher than that of the drift layer is formed between the SiC substrate and the buffer layer so as to be in contact with an upper surface of the SiC substrate.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: June 8, 2021
    Assignee: Hitachi Metals, Ltd.
    Inventors: Kumiko Konishi, Kiyoshi Oouchi, Keisuke Kobayashi, Akio Shima
  • Patent number: 10983424
    Abstract: An image projection apparatus configured to project a projection image on a projected surface via a projection optical system that includes a first optical system capable of adjusting a curvature amount of an image plane and is interchangeably attached to the image projection apparatus includes an acquirer configured to acquire information on a reference position of the first optical system, and a controller configured to move the first optical system to the reference position when detecting an interchange of the projection optical system or when accepting an instruction from a user.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: April 20, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Keisuke Kobayashi
  • Patent number: 10638103
    Abstract: An image projection apparatus displays includes a lens attachable portion to which a plurality of projection lenses having different optical characteristics are interchangeably attached, a drive signal producer configured to produce, for each color light beam, a drive signal used to drive the light modulation element based on an input image signal, and an information acquirer configured to acquire information on an optical characteristic of the projection lens attached to the lens attachable portion. The information on the optical characteristic of the projection lens contains information on a chromatic aberration of the projection lens. The drive signal producer reduces influence of a shift below the modulation pixel caused by the chromatic aberration of the projection lens by using the information on the optical characteristic, and produces the drive signal corresponding to at least one of the plurality of color light beams.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: April 28, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Keisuke Kobayashi
  • Publication number: 20200006066
    Abstract: In a silicon carbide stacked substrate, the efficiency of converting the basal plane dislocation (BPD) which is a fault to deteriorate the current-carrying reliability into a threading edge dislocation (TED) which is a harmless fault is improved, thereby improving the reliability of the silicon carbide stacked substrate. As means therefor, in a silicon carbide stacked substrate including a SiC substrate and a buffer layer and a drift layer which are epitaxial layers sequentially formed on the SiC substrate, a semiconductor layer having an impurity concentration lower than those of the SiC substrate and the buffer layer and higher than that of the drift layer is formed between the SiC substrate and the buffer layer so as to be in contact with an upper surface of the SiC substrate.
    Type: Application
    Filed: January 30, 2018
    Publication date: January 2, 2020
    Inventors: Kumiko KONISHI, Kiyoshi OOUCHI, Keisuke KOBAYASHI, Akio SHIMA
  • Patent number: 10466574
    Abstract: An image projection apparatus includes an acquirer configured to acquire information on a lens unit, and a controller configured to set, based on the information on the lens unit, at least one of an image orientation of a projection image and a shift direction of the lens unit.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: November 5, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Keisuke Kobayashi
  • Publication number: 20190313066
    Abstract: An image projection apparatus configured to project a projection image on a projected surface via a projection optical system that includes a first optical system capable of adjusting a curvature amount of an image plane and is interchangeably attached to the image projection apparatus includes an acquirer configured to acquire information on a reference position of the first optical system, and a controller configured to move the first optical system to the reference position when detecting an interchange of the projection optical system or when accepting an instruction from a user.
    Type: Application
    Filed: April 10, 2019
    Publication date: October 10, 2019
    Inventor: Keisuke Kobayashi
  • Patent number: 10229974
    Abstract: To solve a problem of realizing a large current and highly reliable power semiconductor device while shrinking a unit cell. A semiconductor device according to the present invention includes a plurality of p-type body regions extending in a first direction. The semiconductor device further includes: a JFET region formed to extend in the first direction between p-type body regions which are adjacent to each other in a second direction orthogonal to the first direction; an n+-type source region formed to extend in the first direction within a p-type body region and separate from an end side surface of the p-type body; and a channel region formed to extend in the first direction and in a top layer portion of a p-type body region between an end side surface of the p-type body region and an end side surface of an n+-type source region.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: March 12, 2019
    Assignee: HITACHI, LTD.
    Inventors: Mieko Matsumura, Junichi Sakano, Naoki Tega, Yuki Mori, Haruka Shimizu, Keisuke Kobayashi
  • Publication number: 20190025677
    Abstract: An image projection apparatus includes an acquirer configured to acquire information on a lens unit, and a controller configured to set, based on the information on the lens unit, at least one of an image orientation of a projection image and a shift direction of the lens unit.
    Type: Application
    Filed: July 17, 2018
    Publication date: January 24, 2019
    Inventor: Keisuke Kobayashi
  • Publication number: 20180262728
    Abstract: An image projection apparatus displays includes a lens attachable portion to which a plurality of projection lenses having different optical characteristics are interchangeably attached, a drive signal producer configured to produce, for each color light beam, a drive signal used to drive the light modulation element based on an input image signal, and an information acquirer configured to acquire information on an optical characteristic of the projection lens attached to the lens attachable portion. The information on the optical characteristic of the projection lens contains information on a chromatic aberration of the projection lens. The drive signal producer reduces influence of a shift below the modulation pixel caused by the chromatic aberration of the projection lens by using the information on the optical characteristic, and produces the drive signal corresponding to at least one of the plurality of color light beams.
    Type: Application
    Filed: March 8, 2018
    Publication date: September 13, 2018
    Inventor: Keisuke Kobayashi
  • Patent number: 10066364
    Abstract: A construction machine includes: a cover that covers an engine and a radiator; a radiator fan that is arranged at the rear of a vehicle body frame and discharges exhaust gas toward the rear of the vehicle body frame from the inner space of the cover; an injection device that injects a reducing agent into exhaust gas of the engine; a tank housing section that is arranged at one side of the vehicle body frame, includes an introduction section for introducing outside air, and houses a tank for storing the reducing agent injected by the injection device; and a connection section that is arranged in either the cover or the vehicle body frame and in the tank housing section, connects the inner space of the tank housing section and the inner space of the cover, and allows the outside air and the pipe to pass therethrough, the outside air having been introduced from the introduction section by the suction pressure of the radiator fan, the pipe supplying the reducing agent to the injection device.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: September 4, 2018
    Assignee: KCM Corporation
    Inventors: Yasuo Yamazaki, Takashi Takeyama, Keigo Kikuchi, Akira Shimohira, Keisuke Kobayashi
  • Patent number: 10062759
    Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: August 28, 2018
    Assignee: HITACHI, LTD.
    Inventors: Digh Hisamoto, Keisuke Kobayashi, Naoki Tega, Toshiyuki Ohno, Hirotaka Hamamura, Mieko Matsumura
  • Patent number: 10032871
    Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: July 24, 2018
    Assignee: HITACHI, LTD.
    Inventors: Digh Hisamoto, Keisuke Kobayashi, Naoki Tega, Toshiyuki Ohno, Hirotaka Hamamura, Mieko Matsumura
  • Patent number: 9945099
    Abstract: An industrial vehicle includes: an exhaust gas treatment device arranged in an engine room so as to be located above an engine, the exhaust gas treatment device including a pretreatment unit accommodating a diesel oxidation catalyst and extending in the forward/rearward direction, a selective catalytic reduction unit located adjacent to the pretreatment unit and extending in the forward/rearward direction, a connecting pipe including a mix portion, a first bent portion, and a second bent portion, the mix portion being located between the pretreatment unit and the selective catalytic reduction unit and extending in the forward/rearward direction, the first bent portion connecting the mix portion and an outlet of the pretreatment unit, the outlet being located close to a dividing wall, the second bent portion connecting the mix portion and an inlet of the selective catalytic reduction unit, the inlet being located far from the dividing wall, and a urea water injection device attached to the first bent portion o
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: April 17, 2018
    Assignee: KCM Corporation
    Inventors: Hiroyuki Ishida, Keisuke Kobayashi, Takatomo Ohno, Atsushi Kondo, Tadahiro Miyagawa
  • Publication number: 20180090574
    Abstract: To solve a problem of realizing a large current and highly reliable power semiconductor device while shrinking a unit cell. A semiconductor device according to the present invention includes a plurality of p-type body regions extending in a first direction. The semiconductor device further includes: a JFET region formed to extend in the first direction between p-type body regions which are adjacent to each other in a second direction orthogonal to the first direction; an n+-type source region formed to extend in the first direction within a p-type body region and separate from an end side surface of the p-type body; and a channel region formed to extend in the first direction and in a top layer portion of a p-type body region between an end side surface of the p-type body region and an end side surface of an n+-type source region.
    Type: Application
    Filed: May 18, 2015
    Publication date: March 29, 2018
    Inventors: Mieko MATSUMURA, Junichi SAKANO, Naoki TEGA, Yuki MORI, Haruka SHIMIZU, Keisuke KOBAYASHI