Patents by Inventor Keisuke Otsuka

Keisuke Otsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11952042
    Abstract: A lower vehicle-body structure of a vehicle may include: a floor panel; a side sill; and a frame member that extends in the front-rear direction on the vehicle-width-direction inner side of the side sill and includes a front-rear extended portion that is in abutment against the side sill on the vehicle-width-direction inner side and extends in the vehicle front-rear direction along the side sill. The front-rear extended portion may include: a bottom face portion; an inner wall portion; and an inner-side flange that extends to the vehicle-width-direction inner side from a distal end portion of the inner wall portion and is joined to the floor panel. Deformation facilitating facilitators that facilitate deformation of the bottom face portion in the vehicle width direction when a collision load in the vehicle width direction is input may be formed in the bottom face portion.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: April 9, 2024
    Assignee: MAZDA MOTOR CORPORATION
    Inventors: Mikado Kawasaki, Hirotaka Natsume, Keisuke Ebisumoto, Akiko Nakamoto, Daisuke Tsuji, Kento Otsuka
  • Patent number: 11798837
    Abstract: Methods for forming openings in conductive layers and using the same are described. An example method includes: forming a conductive layer; forming a first hard mask on the conductive layer; forming a second hard mask on the first hard mask; providing an opening through the first and second masks; and removing a surface of the conductive layer under the opening. The first hard mask may have hardness greater than hardness of the second hard mask.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: October 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Tsuyoshi Tomoyama, Keisuke Otsuka
  • Publication number: 20230269930
    Abstract: An apparatus includes: a substrate; a plurality of pillar-shaped bottom electrodes provided over the substrate; and an upper electrode covering side and top surfaces of the pillar-shaped bottom electrodes with an intervening capacitor insulating film therebetween. The pillar-shaped bottom electrodes have at least an upper portion and a lower portion. The diameter of the upper portion is smaller than the diameter of the lower portion.
    Type: Application
    Filed: May 2, 2023
    Publication date: August 24, 2023
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Akira Kaneko, Keisuke Otsuka
  • Patent number: 11647624
    Abstract: An apparatus includes: a substrate; a plurality of pillar-shaped bottom electrodes provided over the substrate; and an upper electrode covering side and top surfaces of the pillar-shaped bottom electrodes with an intervening capacitor insulating film therebetween; wherein the pillar-shaped bottom electrodes have at least an upper portion and a lower portion, and the diameter of the upper portion is smaller than the diameter of the lower portion.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: May 9, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Akira Kaneko, Keisuke Otsuka
  • Publication number: 20230107365
    Abstract: Methods for forming openings in conductive layers and using the same are described. An example method includes: forming a conductive layer; forming a first hard mask on the conductive layer; forming a second hard mask on the first hard mask; providing an opening through the first and second masks; and removing a surface of the conductive layer under the opening. The first hard mask may have hardness greater than hardness of the second hard mask.
    Type: Application
    Filed: October 1, 2021
    Publication date: April 6, 2023
    Applicant: Micron Technology, Inc.
    Inventors: TSUYOSHI TOMOYAMA, KEISUKE OTSUKA
  • Publication number: 20230010901
    Abstract: Disclosed herein is an apparatus that includes a plurality of cell capacitors arranged in a memory cell array region of a semiconductor substrate, each of the plurality of cell capacitors having a first electrode, a second electrode and an insulating film therebetween to electrically disconnect the first and second electrodes, a first conductive member including the plurality of cell capacitors therein, the first conductive member being electrically connected in common to the first electrodes of the plurality of cell capacitors, and a second conductive member formed on an upper surface of the first conductive member, a material of the second conductive member being different from that of the first conductive member. A side surface of the first conductive member is free from the second conductive member.
    Type: Application
    Filed: July 9, 2021
    Publication date: January 12, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Yosuke Adachi, Hiroshi Amaike, Keisuke Otsuka, Shogo Omiya, Tomohiro Iwaki, Emi Seko
  • Publication number: 20220189960
    Abstract: An apparatus includes: a substrate; a plurality of pillar-shaped bottom electrodes provided over the substrate; and an upper electrode covering side and top surfaces of the pillar-shaped bottom electrodes with an intervening capacitor insulating film therebetween; wherein the pillar-shaped bottom electrodes have at least an upper portion and a lower portion, and the diameter of the upper portion is smaller than the diameter of the lower portion.
    Type: Application
    Filed: December 15, 2020
    Publication date: June 16, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Akira Kaneko, Keisuke Otsuka
  • Publication number: 20150333117
    Abstract: One semiconductor device includes lower electrodes arranged in rows along first and second directions parallel to the surface of a semiconductor substrate and extending in a third direction perpendicular to the surface of the substrate, a first support film arranged on the upper end of the lower electrodes and having first openings, a second support film arranged in the middle of the lower electrodes in the third direction, and having second openings aligned in a plane in the same pattern as the first openings, a capacitance insulating film covering the surface of the lower electrodes, and upper electrodes covering the surface of the capacitance insulating film. A portion of each of eight lower electrodes contained in two lower electrode unit groups adjacent in the first direction are collectively positioned inside of the first and second openings. A lower electrode unit group is four lower electrodes adjacent in the second direction.
    Type: Application
    Filed: December 10, 2013
    Publication date: November 19, 2015
    Inventors: Nobuyuki Sako, Eiji Hasunuma, Keisuke Otsuka
  • Publication number: 20150325636
    Abstract: The present invention is characterized by including a plurality of capacitors provided with: a plurality of lower electrodes which extend in a third direction orthogonal to a semiconductor substrate surface; a support film which is positioned flatly and in a manner so as to connect to the upper ends of the outer peripheral side surfaces of the lower electrodes, and which has openings that contain the plurality of lower electrodes; a capacitance insulating film which covers a surface of the lower electrodes; and an upper electrode which covers a surface of the capacitance insulating film.
    Type: Application
    Filed: November 29, 2013
    Publication date: November 12, 2015
    Inventor: Keisuke OTSUKA
  • Patent number: 8633073
    Abstract: A method of forming a semiconductor device includes the following processes. A first groove is formed in a semiconductor substrate. A first conductive film is formed in the first groove and over the semiconductor substrate. The first conductive film is planarized over the semiconductor substrate. The planarized first conductive film is selectively etched to have the planarized first conductive film remain in a lower portion of the first groove.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: January 21, 2014
    Inventor: Keisuke Otsuka
  • Publication number: 20130270677
    Abstract: A semiconductor device includes a semiconductor substrate having a principal surface, a first conductor formed on the semiconductor substrate and including a conductive film having a first side wall portion and a first bottom surface portion both of which are continuously formed on a first trench having a first width in a direction parallel to the principal surface, and a second conductor formed on the semiconductor substrate and including a conductive film having a second side wall portion and a second bottom surface portion both of which are continuously formed on a second trench having a second width in a direction parallel to the principal surface, the second width being larger than the first width.
    Type: Application
    Filed: June 10, 2013
    Publication date: October 17, 2013
    Applicant: Elpida Memory, Inc.
    Inventors: Tsuyoshi Tomoyama, Keisuke Otsuka
  • Publication number: 20130029467
    Abstract: A method of forming a semiconductor device includes the following processes. A first groove is formed in a semiconductor substrate. A first conductive film is formed in the first groove and over the semiconductor substrate. The first conductive film is planarized over the semiconductor substrate. The planarized first conductive film is selectively etched to have the planarized first conductive film remain in a lower portion of the first groove.
    Type: Application
    Filed: October 21, 2011
    Publication date: January 31, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Keisuke OTSUKA
  • Publication number: 20110169061
    Abstract: The semiconductor device comprises a first region, a guard ring surrounding the first region, and a second region outside of the guard ring. The first region includes a first electrode made of a first film which has conductivity. A surface of the first electrode in the first region is not covered with the second film. The guard ring includes the first film covering an inner wall of a groove having a recess shape, and a second film as an insulating film covering at least one portion of a surface of the first film in the groove.
    Type: Application
    Filed: November 24, 2010
    Publication date: July 14, 2011
    Applicant: Elpida Memory, Inc.
    Inventors: Mitsunari Sukekawa, Keisuke Otsuka
  • Publication number: 20110117718
    Abstract: A method of forming a semiconductor device includes forming a hole in an insulating film, forming a first conductive film in the hole, removing at least a portion of the insulating film around the first conductive film, and reducing a thickness of the first conductive film to produce a second conductive film.
    Type: Application
    Filed: November 30, 2009
    Publication date: May 19, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yoshitaka Nakamura, Takahiro Suzuki, Kazuo Nomura, Keisuke Otsuka
  • Publication number: 20100258907
    Abstract: An exemplary aspect of the invention provides a novel semiconductor device and a method for manufacturing the same.
    Type: Application
    Filed: April 5, 2010
    Publication date: October 14, 2010
    Applicant: Elpida Memory, Inc.
    Inventors: Tsuyoshi Tomoyama, Keisuke Otsuka
  • Publication number: 20100248456
    Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first etching process is performed to etch a layer using a resist mask and a hard mask. The resist mask covers the hard mask. The hard mask covers the layer. Then, a second etching process is performed to etch the layer using the hard mask, substantially in the absence of the resist mask.
    Type: Application
    Filed: March 24, 2010
    Publication date: September 30, 2010
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Keisuke Otsuka
  • Patent number: 7617047
    Abstract: A map information system is provided which includes an electronic pen which reads a dot pattern in a form where map images are shown, to output handwriting information, and a processing unit including an association module which associates the output handwriting information with one of the map images where the handwriting information is written and stores it in a storage unit, a search module which searches for the associated handwriting information and map image using information to specify the map image as a search key, a pattern assignment module which when acquiring print request information including information to specify the map images to be printed, newly assigns a dot pattern, and an output instruction module which issues an output instruction so as to cause an output unit to visually output data including the retrieved associated handwriting information and map image and the newly assigned dot pattern.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: November 10, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Hiroko Sakamoto, Yosuke Nitta, Masumi Sato, Keisuke Otsuka
  • Publication number: 20070129887
    Abstract: A map information system is provided which includes an electronic pen which reads a dot pattern in a form where map images are shown, to output handwriting information, and a processing unit including an association module which associates the output handwriting information with one of the map images where the handwriting information is written and stores it in a storage unit, a search module which searches for the associated handwriting information and map image using information to specify the map image as a search key, a pattern assignment module which when acquiring print request information including information to specify the map images to be printed, newly assigns a dot pattern, and an output instruction module which issues an output instruction so as to cause an output unit to visually output data including the retrieved associated handwriting information and map image and the newly assigned dot pattern.
    Type: Application
    Filed: May 25, 2006
    Publication date: June 7, 2007
    Inventors: Hiroko Sakamoto, Yosuke Nitta, Masumi Sato, Keisuke Otsuka