Patents by Inventor Keisuke Yonehama
Keisuke Yonehama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190088342Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series; a plurality of word lines commonly connected to the memory strings and connected to the memory cells; and a control circuit which executes a write operation including a plurality of program loops, each of the program loops including a program operation and a verify operation. When a suspend command for instructing an operation suspend is externally received during execution of the program operation, the control circuit executes a dummy read operation in which the word lines are applied with a voltage after the program operation, and enters into a suspend mode after the dummy read operation.Type: ApplicationFiled: March 9, 2018Publication date: March 21, 2019Applicant: Toshiba Memory CorporationInventors: Yasuhiro SHIMURA, Shinichi Oosera, Junichi Kijima, Tomoki Higashi, Sumito Ohtsuki, Tomohiro Oda, Keisuke Yonehama
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Publication number: 20180342300Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: ApplicationFiled: August 7, 2018Publication date: November 29, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
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Publication number: 20180268906Abstract: According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.Type: ApplicationFiled: September 8, 2017Publication date: September 20, 2018Applicant: Toshiba Memory CorporationInventors: Yasuhiro SHIMURA, Tomoki HIGASHI, Sumito OHTSUKI, Junichi KIJIMA, Keisuke YONEHAMA, Shinichi OOSERA, Yuki KANAMORI, Hidehiro SHIGA, Koki UENO
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Patent number: 10074434Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: GrantFiled: October 23, 2017Date of Patent: September 11, 2018Assignee: Toshiba Memory CorporationInventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
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Publication number: 20180175055Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: ApplicationFiled: February 12, 2018Publication date: June 21, 2018Inventors: Toshifumi MINAMI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA, Hideyuki KAMATA, Teppei HIGASHITSUJI
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Publication number: 20180108418Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: ApplicationFiled: October 23, 2017Publication date: April 19, 2018Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
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Patent number: 9893078Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: GrantFiled: February 24, 2015Date of Patent: February 13, 2018Assignee: Toshiba Memory CorporationInventors: Toshifumi Minami, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara, Hideyuki Kamata, Teppei Higashitsuji
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Patent number: 9799403Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: GrantFiled: June 6, 2016Date of Patent: October 24, 2017Assignee: Toshiba Memory CorporationInventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
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Patent number: 9768189Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.Type: GrantFiled: April 7, 2016Date of Patent: September 19, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroshi Shinohara, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Toshifumi Minami, Hiroyuki Maeda, Shinji Saito, Hideyuki Kamata
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Publication number: 20160358659Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: ApplicationFiled: June 6, 2016Publication date: December 8, 2016Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
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Patent number: 9437300Abstract: A semiconductor memory device includes first and second memory cell transistors, first and second word lines electrically connected to the first and second memory cell transistors, respectively, first and second transfer transistors. The first and second transistors are electrically connected to the first and second word lines, respectively. The sizes of the first transistor and the second transistor are different.Type: GrantFiled: August 26, 2014Date of Patent: September 6, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hideyuki Kamata, Toshifumi Minami, Teppei Higashitsuji, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara
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Publication number: 20160218109Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.Type: ApplicationFiled: April 7, 2016Publication date: July 28, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi SHINOHARA, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Toshifumi Minami, Hiroyuki Maeda, Shinji Saito, Hideyuki Kamata
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Patent number: 9361988Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: GrantFiled: August 26, 2014Date of Patent: June 7, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
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Patent number: 9337145Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.Type: GrantFiled: March 10, 2015Date of Patent: May 10, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Shinohara, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Toshifumi Minami, Hiroyuki Maeda, Shinji Saito, Hideyuki Kamata
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Publication number: 20160071870Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: ApplicationFiled: February 24, 2015Publication date: March 10, 2016Inventors: Toshifumi MINAMI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA, Hideyuki KAMATA, Teppei HIGASHITSUJI
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Publication number: 20160071793Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.Type: ApplicationFiled: March 10, 2015Publication date: March 10, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi SHINOHARA, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Toshifumi MINAMI, Hiroyuki MAEDA, Shinji SAITO, Hideyuki KAMATA
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Publication number: 20150262669Abstract: A semiconductor memory device includes first and second memory cell transistors, first and second word lines electrically connected to the first and second memory cell transistors, respectively, first and second transfer transistors. The first and second transistors are electrically connected to the first and second word lines, respectively. The sizes of the first transistor and the second transistor are different.Type: ApplicationFiled: August 26, 2014Publication date: September 17, 2015Inventors: Hideyuki KAMATA, Toshifumi MINAMI, Teppei HIGASHITSUJI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA
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Publication number: 20150262685Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: ApplicationFiled: August 26, 2014Publication date: September 17, 2015Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
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Publication number: 20150062843Abstract: According to one embodiment, a semiconductor device includes a cell portion and a peripheral portion, including: a substrate, a first insulating layer disposed on the substrate, a first conductive layer disposed on the first insulating layer, a second insulating layer disposed on the first conductive layer, and a second conductive layer disposed on the second insulating layer.Type: ApplicationFiled: March 12, 2014Publication date: March 5, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Teppei HIGASHITSUJI, Toshifumi MINAMI, Hideyuki KAMATA, Atsuhiro SATO, Keisuke YONEHAMA
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Patent number: 8502321Abstract: A semiconductor device including first and second transistors having first and second gates and first and second source/drain regions, respectively. First and second contacts are electrically connected to the first and the second source/drain regions, respectively. A width of a first bottom surface of the first contacts in a gate width direction of the first-gate is wider than a width of the first bottom surface in a gate length direction of the first-gate. Widths of a second bottom surface of the second-contact are narrower than a longitudinal direction width of the first bottom surface. A high-concentration region is formed between the first source/drain regions and the first-contact. Extending widths of an outline of the high-concentration region extending from an outline of the first bottom surface in the longitudinal direction are larger than extending widths of an outline of the high-concentration region extending from an outline thereof in the short direction.Type: GrantFiled: March 22, 2011Date of Patent: August 6, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Izumi, Kikuko Sugimae, Hiroyuki Kutsukake, Keisuke Yonehama