Abstract: A method for manufacturing a transistor includes providing a transistor assembly having a semiconductor layer with a first surface, a dielectric layer disposed on the first surface, a gate electrode disposed on the dielectric layer, an insulation layer adjacent at least part of the gate electrode, and a nitride spacer layer adjacent at least part of the insulation layer. The method also includes depositing, on part of the first surface, a material that will react with the semiconductor layer to form silicide and removing the unreacted material. The method further includes etching the nitride spacer layer, depositing a pre-metal spacer layer adjacent at least part of the nitride spacer layer and at least part of the first surface, etch removing a portion of the pre-metal spacer layer to expose part of the silicided portion of the first surface, and forming a contact with the silicided portion of the first surface.

Abstract: Methods and apparatus are disclosed for selectively inducing stress in a semiconductor device, wherein a first region of a substrate is implanted so as to induce stress in a second region. An electrical device is formed at least partially in the second region, wherein the induced stress therein may improve one or more operational characteristics of the device, such as channel region carrier mobility.

Abstract: A method for forming a SOI structure in which porous silicon is sealed and an epitaxial layer is grown thereover, followed by implantation of oxygen and annealing.

Abstract: Methods and apparatus are disclosed for selectively inducing stress in a semiconductor device, wherein a first region of a substrate is implanted so as to induce stress in a second region. An electrical device is formed at least partially in the second region, wherein the induced stress therein may improve one or more operational characteristics of the device, such as channel region carrier mobility.

Abstract: A method for manufacturing a transistor includes providing a transistor assembly having a semiconductor layer with a first surface, a dielectric layer disposed on the first surface, a gate electrode disposed on the dielectric layer, an insulation layer adjacent at least part of the gate electrode, and a nitride spacer layer adjacent at least part of the insulation layer. The method also includes depositing, on part of the first surface, a material that will react with the semiconductor layer to form silicide and removing the unreacted material. The method further includes etching the nitride spacer layer, depositing a pre-metal spacer layer adjacent at least part of the nitride spacer layer and at least part of the first surface, etch removing a portion of the pre-metal spacer layer to expose part of the silicided portion of the first surface, and forming a contact with the silicided portion of the first surface.

Abstract: Methods and apparatus are disclosed for selectively inducing stress in a semiconductor device, wherein a first region of a substrate is implanted so as to induce stress in a second region. An electrical device is formed at least partially in the second region, wherein the induced stress therein may improve one or more operational characteristics of the device, such as channel region carrier mobility.

Abstract: A semiconductor device and a method for making it involve the semiconductor device (10, 110, 210, 310) having a substrate (11, 311) with spaced source and drain regions (13-14, 316-318, 321-323). A gate section (21) projects upwardly from between an adjacent pair of these regions, into an insulating layer (46, 363). In order to create local interconnects to the source and drain regions through the insulating layer, a patterned etch is carried out using an etch region (51), which extends over one of the gate sections from a location above one of the regions to a location above another of the regions. Etching in this etch region produces recesses (56-57) on opposite sides of and immediately adjacent the gate section. A conductive layer (61, 120) is deposited to fill the recesses, and then is planarized back to the upper ends of the gate sections.

Abstract: Transistor isolation is improved by eliminating the channeling tail of an N well implant. To do this, a low dose, high energy implant of an oppositely charged dopant ion is implanted, targeted at the depth of the channeling tail.

Abstract: A method for manufacturing a transistor includes providing a transistor assembly having a semiconductor layer with a first surface, a dielectric layer disposed on the first surface, a gate electrode disposed on the dielectric layer, an insulation layer adjacent at least part of the gate electrode, and a nitride spacer layer adjacent at least part of the insulation layer. The method also includes depositing, on part of the first surface, a material that will react with the semiconductor layer to form silicide and removing the unreacted material. The method further includes etching the nitride spacer layer, depositing a pre-metal spacer layer adjacent at least part of the nitride spacer layer and at least part of the first surface, etch removing a portion of the pre-metal spacer layer to expose part of the silicided portion of the first surface, and forming a contact with the silicided portion of the first surface.

Abstract: A semiconductor device and a method for making it involve the semiconductor device (10, 110, 210, 310) having a substrate (11, 311) with spaced source and drain regions (13-14, 316-318, 321-323). A gate section (21) projects upwardly from between an adjacent pair of these regions, into an insulating layer (46, 363). In order to create local interconnects to the source and drain regions through the insulating layer, a patterned etch is carried out using an etch region (51), which extends over one of the gate sections from a location above one of the regions to a location above another of the regions. Etching in this etch region produces recesses (56-57) on opposite sides of and immediately adjacent the gate section. A conductive layer (61, 120) is deposited to fill the recesses, and then is planarized back to the upper ends of the gate sections.

Abstract: Methods and apparatus are disclosed for selectively inducing stress in a semiconductor device, wherein a first region of a substrate is implanted so as to induce stress in a second region. An electrical device is formed at least partially in the second region, wherein the induced stress therein may improve one or more operational characteristics of the device, such as channel region carrier mobility.

Abstract: A method for manufacturing a transistor includes providing a transistor assembly having a semiconductor layer with a first surface, a dielectric layer disposed on the first surface, a gate electrode disposed on the dielectric layer, an insulation layer adjacent at least part of the gate electrode, and a nitride spacer layer adjacent at least part of the insulation layer. The method also includes depositing, on part of the first surface, a material that will react with the semiconductor layer to form silicide and removing the unreacted material. The method further includes etching the nitride spacer layer, depositing a pre-metal spacer layer adjacent at least part of the nitride spacer layer and at least part of the first surface, etch removing a portion of the pre-metal spacer layer to expose part of the silicided portion of the first surface, and forming a contact with the silicided portion of the first surface.

Abstract: A method for forming a SOI structure in which porous silicon is sealed and an epitaxial layer is grown thereover, followed by implantation of oxygen and annealing.

Abstract: Transistor isolation is improved by eliminating the channeling tail of an N well implant. To do this, a low dose, high energy implant of an oppositely charged dopant ion is implanted, targeted at the depth of the channeling tail.

Abstract: Varying the porosity through the thickness of a porous silicon layer allows conflicting needs to be met by the same layer: a low porosity surface layer allows a high-quality epitaxial layer of silicon to be grown, or can provide structural support, while greater porosity in other portions of the layer increases circuit isolation and provides stress relief between layers.

Abstract: An epitaxial layer of silicon is grown on a layer of partially-oxidized porous silicon, then covered by a capping layer which provides structural support and prevents oxidation of the epitaxial layer. A high-temperature anneal allows the partially oxidized silicon layer to separate into distinct layers of silicon and SiO2, producing a buried oxide layer. This method provides a low cost means of producing silicon-on-insulator (SOI) wafers.

Abstract: Disposable spacers of an organic material or a low-temperature inorganic material provide advantages in the formation of STI trenches and contact holes and additional freedom in line spacing.

Abstract: In order to form an isolation structure in a substrate, a blocking layer (13, 14) is fabricated over the substrate (12), after which portions of the blocking layer and the substrate are removed at an isolation region (22). A dielectric layer (26) is then deposited over the blocking layer and the isolation region. Thereafter, a chemical-mechanical polishing process is carried out on the dielectric layer, so as to remove a substantial portion of the dielectric layer disposed above an upper surface of the blocking layer. A non-patterned etch is then carried out on the dielectric layer, in order to remove a remaining portion of the dielectric layer disposed above the upper surface of the blocking layer.

Abstract: A transistor (100) having a strip channel or channels (108) in which the current flow in is the lateral direction between source (110) and drain (112). The gate (116) is located on the sidewalls and, if desired, the top of the strip channel (108). In a preferred embodiment of the invention, a disposable gate process is used that allows the source (110) and drain (112) regions to be self-aligned to the gate (116).

Abstract: An isolation structure is provided that includes a substrate (10), a refill material such as a refill oxide (22), a gate dielectric such as a gate oxide layer (24), and a gate conductor layer such a polysilicon gate layer (26). The substrate (10) has an active region (12), an active region (14), and a trench region provided between the active region (12) and the active region (14). The active region (14) includes a top corner (32) that is provided where an upper surface of the active region (14) and the trench wall of the trench region that is adjacent to the active region (14) meet. The refill oxide (22) is positioned within the trench region and extends to cover at least a portion of the top corner. The gate oxide layer (24) is provided on the upper surface of the active region (14). The polysilicon gate layer (26) is provided on an upper surface of the gate oxide layer (24).