Abstract: A semiconductor device and method having mesas with uniformly-doped regions 18. A semiconductor substrate 10 is uniformly-doped and then, mesas 12 are formed in the semiconductor surface. Advantages of the invention include a mesa 12 having a uniformly-doped surface, solving the problem of non-uniformity of doping density caused by lateral ion straggling found in the prior art. Another advantage of the invention is a structure having evenly-doped mesas yet undoped trenches.

Abstract: A transistor (100) having a strip channel or channels (108) in which the current flow in is the lateral direction between source (110) and drain (112). The gate (116) is located on the sidewalls and, if desired, the top of the strip channel (108). In a preferred embodiment of the invention, a disposable gate process is used that allows the source (110) and drain (112) regions to be self-aligned to the gate (116).

Abstract: An isolation structure is provided that includes a substrate (10), a refill material such as a refill oxide (22), a gate dielectric such as a gate oxide layer (24), and a gate conductor layer such a polysilicon gate layer (26). The substrate (10) has an active region (12), an active region (14), and a trench region provided between the active region (12) and the active region (14). The active region (14) includes a top corner (32) that is provided where an upper surface of the active region (14) and the trench wall of the trench region that is adjacent to the active region (14) meet. The refill oxide (22) is positioned within the trench region and extends to cover at least a portion of the top corner. The gate oxide layer (24) is provided on the upper surface of the active region (14). The polysilicon gate layer (26) is provided on an upper surface of the gate oxide layer (24).

Abstract: A silicon-on-insulator trench isolation structure is disclosed that includes an active silicon-on-insulator region, an active bulk substrate region, and a trench region positioned between the active silicon-on-insulator region and the active bulk substrate region. The active silicon-on-insulator region is provided with a silicon-on-insulator film (42) positioned above a buried insulator layer (32). The active bulk substrate region may be provided between two trench regions such as a trench region (20) and a trench region (22). The trench region (20) is positioned between the active silicon-on-insulator region and the active bulk substrate region.

Abstract: A method of forming silicided narrow (i.e., sub-0.25 .mu.m) polysilicon lines. A layer of titanium is deposited over a semiconductor body having polysilicon lines formed thereon Either before or after the titanium deposition and before the react step, an implant is performed using a gas that will not poison the subsequent silicidation reaction. Exemplary gases include the noble element gases such as argon, krypton, xenon, and neon. The titanium is then reacted with the polysilicon lines to form titanium silicide. The gas implant causes the C49 grain size of the titanium silicide to be reduced, which makes the transformation to the C54 phase easier. Finally, an anneal is performed to transform the titanium silicide from the C49 phase to the C54 phase.

Abstract: An active silicon-on-insulator region isolation structure is provided that includes an active bulk substrate region (24), an active silicon-on-insulator region (22), and a transition region positioned between the active bulk substrate region (24) and the active silicon-on-insulator region (22). The active silicon-on-insulator region (22) includes a silicon-on-insulator film (16) positioned above a buried insulator layer (18). The transition region includes a sloping portion of the buried insulator layer (18) and a tapered edge portion of the silicon-on-insulator film (16).

Abstract: A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to "dishing" that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.

Abstract: After formation of a sandwich over a substrate of a layer of silicon dioxide (3) followed by a layer of silicon (1) having a pad oxide (7) thereon and a patterned silicon nitride layer (9) over the pad oxide, the unmasked portion of the pad oxide and silicon are removed to provide mesas of silicon with silicon nitride thereover and possibly removal of some of the buried oxide layer. A flowable insulator (15), preferably silsesquioxane (H.sub.x SiO.sub.1.5, where x.ltoreq.1, depending upon the level of polymerization) in a contaminant-free, high purity solvent which is later removed during an annealing step, is placed over the exposed surface such that it fills the voids between the mesas of silicon with silicon nitride thereon and extends over the nitride. The flowable insulator, due to its flowability, provides a generally planar surface. The flowable insulator is etched back and a cap oxide (17) is optionally deposited over the etched back insulator layer.

Abstract: A shallow trench isolation (STJ) (10) is used to isolate two active regions (12) from each other. The advantage of STI (10) is that the upper corners (14) are rounded. Rounding of the upper corners (14) is accomplished using an oxide deglaze prior to sidewall oxidation of the trench which undercuts the pad oxide (20) from the pad nitride (22). The allows the sidewall oxidation process to form a thicker oxide at upper corners (14) which in turn, rounds the corners. Rounded corners (14) minimum the electric field strength induced by the geometry. As a result, the Vt lowering that occurs in prior art STI structures is minimized and off-state leakage due to the inherent parasitic transistor at the upper corner is reduced.

Abstract: A preferred embodiment of this invention is a silicon-on-insulator structure comprising a semiconductor substrate (e.g. Si 36), a buried insulator layer (e.g. SiO.sub.2 34) overlaying the substrate, wherein the buried layer is buried at two or more predetermined depths, and a surface silicon layer (e.g Si 32) overlaying the buried insulator, wherein the surface silicon layer has two or more predetermined thicknesses. Generally, by patterning and etching a screening material (e.g. SiO.sub.2 30) prior to ion implantation, preselected areas of the substrate with less or no screen material are formed with a thicker surface silicon layer, while other areas with more screen material are formed with a thinner surface silicon layer. The areas of different surface silicon thickness can be used to implement devices with different characteristics based on those thicknesses, within the same integrated circuit.

Abstract: An implantation system (10) is provided that comprises a rotating drum (12) which holds a wafer chuck (28) which in turn holds a semiconductor wafer (26). The wafer chuck (28) rotates during the implantation of oxygen from an oxygen beam (24) created by a beam generator (22). The wafer chuck (28) is rotated via shaft (30) from a motor (32). The wafer chuck (28) also holds a thermal reflector (36) which allows for control of the temperature of the wafer during the implantation process.

Abstract: A method for constructing a semiconductor-on-insulator is provided. A sacrificial layer (12) of a predetermined thickness is first formed on a semiconductor wafer (10) surface. The wafer (10) is then subjected to an ion implantation process to place the ions (16) at predetermined depths below the semiconductor wafer surface. During the implantation process, the sacrificial layer (12) is gradually sputtered away and thereby compensating the gradual outgrowth of the silicon surface due to the volume of the implanted ions (16). A post-implant anneal is performed to allow the ions (16) to react with the semiconductor to form a buried insulating layer (24).

Abstract: A preferred embodiment of this invention is a silicon-on-insulator structure comprising a semiconductor substrate (e.g. Si 36), a buried insulator layer (e.g. SiO.sub.2 34) overlaying the substrate, wherein the buried layer is buried at two or more predetermined depths, and a surface silicon layer (e.g. Si 32) overlaying the buried insulator, wherein the surface silicon layer has two or more predetermined thicknesses. Generally, by patterning and etching a screening material (e.g. SiO.sub.2 30) prior to ion implantation, preselected areas of the substrate with less or no screen material are formed with a thicker surface silicon layer, while other areas with more screen material are formed with a thinner surface silicon layer. The areas of different surface silicon thickness can be used to implement devices with different characteristics based on those thicknesses, within the same integrated circuit.

Abstract: In accordance with the present invention, there is provided a method and structure which substantially reduce the leakage current between the surface layer and the substrate silicon that can be caused by the leakage pipes formed in the buried layer in a SIMOX process. A novel solution to this problem is to etch the silicon in these pipes by using an anodizing process. A preferred embodiment of this invention comprises the steps of exposing the surface layer (e.g. silicon 34) to an electrolytic solution (e.g dilute HF acid 38), and creating a potential difference between the substrate (e.g. silicon 30) and the solution, thereby causing current to flow through the leakage pipes (e.g. silicon 36) in the buried insulator layer (e.g. SiO.sub.

Abstract: Disclosed is a process for depositing a metal film on a silicon oxide or silicon nitride surface. This process provides an extremely adherent metallic film and is resistant to interdiffusion between the semiconductor, the insulator, and the metal. The process includes forming contact openings through an insulating layer to a silicon substrate; sputter etching the insulating layer and exposed substrate; depositing layers of platinum, a barrier metal and a conducting metal; and heating to form platinum silicide in the contact openings. The process is useful in forming an electrical interconnection system on a semiconductor device.