Patents by Inventor Keith E. Fogel

Keith E. Fogel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10672929
    Abstract: A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Keith E. Fogel, Bahman Hekmatshoar-Tabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10651273
    Abstract: A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • Publication number: 20200123677
    Abstract: A structure including a three-dimensionally stretchable single crystalline semiconductor membrane located on a substrate is provided. The structure is formed by providing a three-dimensional (3D) wavy silicon germanium alloy layer on a silicon handler substrate. A single crystalline semiconductor material membrane is then formed on a physically exposed surface of the 3D wavy silicon germanium alloy layer. A substrate is then formed on a physically exposed surface of the single crystalline semiconductor material membrane. The 3D wavy silicon germanium alloy layer and the silicon handler substrate are thereafter removed providing the structure.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Keith E. Fogel
  • Publication number: 20200127132
    Abstract: A semiconductor structure is provided that includes non-metal semiconductor alloy containing contact structures for field effect transistors (FETs), particularly p-type FETs. Notably, each non-metal semiconductor alloy containing contact structure includes a highly doped epitaxial semiconductor material directly contacting a topmost surface of a source/drain region of the FET, a titanium liner located on the highly doped epitaxial semiconductor material, a diffusion barrier liner located on the titanium liner, and a contact metal portion located on the diffusion barrier liner.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Inventors: Veeraraghavan S. Basker, Keith E. Fogel, Nicole S. Munro, Alexander Reznicek
  • Patent number: 10593659
    Abstract: A deep trench capacitor having a high capacity is formed into a deep trench having faceted sidewall surfaces. The deep trench is located in a bulk silicon substrate that contains an upper region of undoped silicon and a lower region of n-doped silicon. The lower region of the bulk silicon substrate includes alternating regions of n-doped silicon that have a first boron concentration (i.e., boron deficient regions), and regions of n-doped silicon that have a second boron concentration which is greater than the first boron concentration (i.e., boron rich regions).
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Keith E. Fogel, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10541202
    Abstract: An antifuse is provided that is embedded in a semiconductor substrate. The antifuse has a large contact area, and a reduced breakdown voltage. After blowing the antifuse, the antifuse has a low resistance. The antifuse may have a single breakdown point or multiple breakdown points. The antifuse includes a metal or metal alloy structure that is separated from a doped semiconductor material portion of the semiconductor substrate by an antifuse dielectric material liner. The metal or metal alloy structure and the antifuse dielectric material liner have topmost surfaces that are coplanar with each other as well as being coplanar with a topmost surface of the semiconductor substrate.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Keith E. Fogel, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10541203
    Abstract: Semiconductor fuses include a semiconductor fin having a metallized region between two non-metallized regions. Conductive layers are formed on the semiconductor fin above the two non-metallized regions. A dielectric layer is formed over the metallized region, between the conductive layers.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Keith E. Fogel, Pouya Hashemi, Alexander Reznicek
  • Publication number: 20190378842
    Abstract: A semiconductor structure is provided in which a nanosheet device is formed laterally adjacent, but in proximity to, an embedded dynamic random access memory (eDRAM) cell. The eDRAM cell and the nanosheet device are connected by a doped polycrystalline semiconductor material that is formed during the epitaxial growth of doped single crystalline semiconductor source/drain regions of the nanosheet device. An eDRAM cut mask is used to remove unwanted semiconductor material from regions not including the eDRAM cell and the nanosheet device.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 12, 2019
    Inventors: Alexander Reznicek, Muthumanickam Sankarapandian, Donald F. Canaperi, Keith E. Fogel
  • Publication number: 20190341528
    Abstract: A light emitting diode (LED) includes a p-type ohmic contact and a p-type substrate in contact with the p-type ohmic contact. A p-type confinement layer is provided on the p-type substrate. An emission layer is provided on the p-type confinement layer. An n-type confinement layer is provided on the emission layer. A transparent II-VI n-type contact layer is formed on the n-type confinement layer as a replacement for a current spreading layer, a III-V contact layer and an n-type ohmic contact.
    Type: Application
    Filed: July 22, 2019
    Publication date: November 7, 2019
    Inventors: Keith E. Fogel, Jeehwan Kim, Ning Li, Devendra K. Sadana
  • Patent number: 10439106
    Abstract: A light emitting diode (LED) includes a p-type ohmic contact and a p-type substrate in contact with the p-type ohmic contact. A p-type confinement layer is provided on the p-type substrate. An emission layer is provided on the p-type confinement layer. An n-type confinement layer is provided on the emission layer. A transparent II-VI n-type contact layer is formed on the n-type confinement layer as a replacement for a current spreading layer, a III-V contact layer and an n-type ohmic contact.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: October 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith E. Fogel, Jeehwan Kim, Ning Li, Devendra K. Sadana
  • Publication number: 20190296113
    Abstract: A method of making a GaN device includes: forming a GaN substrate; forming a plurality of spaced-apart first metal contacts directly on the GaN substrate; forming a layer of insulating GaN on the exposed portions of the upper surface; forming a stressor layer on the contacts and the layer of insulating GaN; forming a handle substrate on the first surface of the stressor layer; spalling the GaN substrate that is located beneath the stressor layer to separate a layer of GaN and removing the handle substrate; bonding the stressor layer to a thermally conductive substrate; forming a plurality of vertical channels through the GaN to define a plurality of device structures; removing the exposed portions of the layer of insulating GaN to electrically isolate the device structures; forming an ohmic contact layer on the second surface; and forming second metal contacts on the ohmic contact layer.
    Type: Application
    Filed: May 29, 2019
    Publication date: September 26, 2019
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Patent number: 10424644
    Abstract: A method of making a GaN device includes: forming a GaN substrate; forming a plurality of spaced-apart first metal contacts directly on the GaN substrate; forming a layer of insulating GaN on the exposed portions of the upper surface; forming a stressor layer on the contacts and the layer of insulating GaN; forming a handle substrate on the first surface of the stressor layer; spalling the GaN substrate that is located beneath the stressor layer to separate a layer of GaN and removing the handle substrate; bonding the stressor layer to a thermally conductive substrate; forming a plurality of vertical channels through the GaN to define a plurality of device structures; removing the exposed portions of the layer of insulating GaN to electrically isolate the device structures; forming an ohmic contact layer on the second surface; and forming second metal contacts on the ohmic contact layer.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Patent number: 10396165
    Abstract: A strain relaxed silicon germanium layer that has a low defect density is formed on a surface of a silicon substrate without causing wafer bowing. The strain relaxed silicon germanium layer is formed using multiple epitaxial growing, bonding and transferring steps. In the present application, a thick silicon germanium layer having a low defect density is grown on a transferred portion of a topmost silicon germanium sub-layer of an initial strain relaxed silicon germanium graded buffer layer and then bonded to a silicon substrate. A portion of the thick silicon germanium layer is then transferred to the silicon substrate. Additional steps of growing a thick silicon germanium layer having a low defect density, bonding and layer transfer may be performed as necessary.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Keith E. Fogel, Alexander Reznicek, Oscar van der Straten
  • Publication number: 20190259886
    Abstract: A photovoltaic device includes a substrate having a plurality of hole shapes formed therein. The plurality of hole shapes each have a hole opening extending from a first surface and narrowing with depth into the substrate. The plurality of hole shapes form a hole pattern on the first surface, and the hole pattern includes flat areas separating the hole shapes on the first surface. A photovoltaic device stack is formed on the first surface and extends into the hole shapes. Methods are also provided.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Inventors: Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Patent number: 10388808
    Abstract: A photovoltaic device includes a substrate having a plurality of hole shapes formed therein. The plurality of hole shapes each have a hole opening extending from a first surface and narrowing with depth into the substrate. The plurality of hole shapes form a hole pattern on the first surface, and the hole pattern includes flat areas separating the hole shapes on the first surface. A photovoltaic device stack is formed on the first surface and extends into the hole shapes. Methods are also provided.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Publication number: 20190237597
    Abstract: A photovoltaic device and method include forming a plurality of pillar structures in a substrate, forming a first electrode layer on the pillar structures and forming a continuous photovoltaic stack including an N-type layer, a P-type layer and an intrinsic layer on the first electrode. A second electrode layer is deposited over the photovoltaic stack such that gaps or fissures occur in the second electrode layer between the pillar structures. The second electrode layer is wet etched to open up the gaps or fissures and reduce the second electrode layer to form a three-dimensional electrode of substantially uniform thickness over the photovoltaic stack.
    Type: Application
    Filed: April 5, 2019
    Publication date: August 1, 2019
    Inventors: KEITH E. FOGEL, AUGUSTIN J. HONG, JEEHWAN KIM, DEVENDRA K. SADANA
  • Patent number: 10366881
    Abstract: A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins. A surface of the porous fins is treated to make the surface suitable for epitaxial growth. Lattice mismatch is compensated for between an epitaxially grown monocrystalline layer grown on the surface and the monocrystalline substrate by relaxing the epitaxially grown monocrystalline layer using the porous fins to form a relaxed heteroepitaxial interface with the monocrystalline substrate.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • Patent number: 10347779
    Abstract: A photovoltaic device and method include forming a plurality of pillar structures in a substrate, forming a first electrode layer on the pillar structures and forming a continuous photovoltaic stack including an N-type layer, a P-type layer and an intrinsic layer on the first electrode. A second electrode layer is deposited over the photovoltaic stack such that gaps or fissures occur in the second electrode layer between the pillar structures. The second electrode layer is wet etched to open up the gaps or fissures and reduce the second electrode layer to form a three-dimensional electrode of substantially uniform thickness over the photovoltaic stack.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Patent number: 10340221
    Abstract: A method and apparatus for forming a semiconductor structure is provided. The semiconductor structure comprises a stacked fin structure formed on a surface of a first insulator layer. The stacked fin structure comprises a first doped semiconductor fin portion and a second doped semiconductor fin portion. The anti-fuse structure further comprises a first highly doped diamond shaped epitaxial structure grown about the first semiconductor fin portion and a second diamond shaped highly doped epitaxial structure grown about the second semiconductor fin portion. The first highly doped epitaxial structure has a lower-most apex overlying and aligned with an upper-most apex of the second highly doped epitaxial structure. The lower-most apex is separated from the upper-most apex by a gap. A second insulating layer formed about the first highly-doped epitaxial structure and the second highly-doped epitaxial structure, wherein the second insulator layer fills the gap.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Oscar Van Der Straten, Praneet Adusumilli, Keith E. Fogel
  • Publication number: 20190198696
    Abstract: A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate.
    Type: Application
    Filed: February 26, 2019
    Publication date: June 27, 2019
    Inventors: Stephen W. Bedell, Keith E. Fogel, Bahman Hekmatshoar-Tabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi