Abstract: A deep trench capacitor having a high capacity is formed into a deep trench having faceted sidewall surfaces. The deep trench is located in a bulk silicon substrate that contains an upper region of undoped silicon and a lower region of n-doped silicon. The lower region of the bulk silicon substrate includes alternating regions of n-doped silicon that have a first boron concentration (i.e., boron deficient regions), and regions of n-doped silicon that have a second boron concentration which is greater than the first boron concentration (i.e., boron rich regions).

Abstract: A deep trench capacitor having a high capacity is formed into a deep trench having faceted sidewall surfaces. The deep trench is located in a bulk silicon substrate that contains an upper region of undoped silicon and a lower region of n-doped silicon. The lower region of the bulk silicon substrate includes alternating regions of n-doped silicon that have a first boron concentration (i.e., boron deficient regions), and regions of n-doped silicon that have a second boron concentration which is greater than the first boron concentration (i.e., boron rich regions).

Abstract: A tensile strained silicon layer and a compressively strained silicon germanium layer are formed on a strain relaxed silicon germanium buffer layer substrate. A relaxed silicon layer is formed on the substrate and the compressively strained silicon germanium layer is formed on the relaxed silicon layer. The compressively strained silicon germanium layer can accordingly have approximately the same concentration of germanium as the underlying strain relaxed buffer layer substrate, which facilitates gate integration. The tensile strained silicon layer and the compressively strained silicon germanium layer can be configured as fins used in the fabrication of FinFET devices. The relaxed silicon layer and a silicon germanium layer underlying the tensile silicon layer can be doped in situ to provide punch through stop regions adjoining the fins.

Abstract: Semiconductor fuses and methods of forming the same include forming a dummy gate on a semiconductor fin. A dielectric layer is formed around the dummy gate. The dummy gate is removed to expose a region of the semiconductor fin. The exposed region is metallized.

Abstract: MIS capacitors are formed using a finned semiconductor structure. A highly doped region including the fins is formed within the structure and forms one plate of a MIS capacitor. A metal layer forms a second capacitor plate that is separated from the first plate by a high-k capacitor dielectric layer formed directly on the highly doped fins. Contacts are electrically connected to the capacitor plates. A highly doped implantation layer having a conductivity type opposite to that of the highly doped region provides electrical isolation within the structure.

Abstract: An antifuse is provided that is embedded in a semiconductor substrate. The antifuse has a large contact area, and a reduced breakdown voltage. After blowing the antifuse, the antifuse has a low resistance. The antifuse may have a single breakdown point or multiple breakdown points. The antifuse includes a metal or metal alloy structure that is separated from a doped semiconductor material portion of the semiconductor substrate by an antifuse dielectric material liner. The metal or metal alloy structure and the antifuse dielectric material liner have topmost surfaces that are coplanar with each other as well as being coplanar with a topmost surface of the semiconductor substrate.

Abstract: A photovoltaic device includes a substrate having a plurality of hole shapes formed therein. The plurality of hole shapes each have a hole opening extending from a first surface and narrowing with depth into the substrate. The plurality of hole shapes form a hole pattern on the first surface, and the hole pattern includes flat areas separating the hole shapes on the first surface. A photovoltaic device stack is formed on the first surface and extends into the hole shapes. Methods are also provided.

Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. A dielectric interlayer is formed on the p-doped layer. An n-type layer is formed on the dielectric interlayer, the n-type layer including a high band gap II-VI material to form an electronic device.

Abstract: A method includes providing a semiconductor substrate having a plurality of linear semiconductor fin structures spaced apart from one another on a surface of the substrate; siliciding sidewalls of the semiconductor fin structures; removing an unsilicided central portion of each semiconductor fin structure leaving, for a given one of the semiconductor fin structures, a pair of silicide fin structures that are parallel to one another and spaced apart from one another by a distance about equal to a width of the removed unsilicided central portion of the semiconductor fin structure; and forming contacts to conductively connect together a plurality of the silicide fin structures to form a resistor. A resistance value of the resistor is related at least to a type of silicide, a number of contacted adjacent silicide fin structures and a length between two contacts.

Abstract: A method of forming a semiconductor on a porous semiconductor structure. The method may include forming a stack, the stack includes (from bottom to top) a substrate, a base silicon layer, a thick silicon layer, and a thin silicon layer, where the thin silicon layer and the thick silicon layer are relaxed; converting the thick silicon layer into a porous silicon layer using a porousification process; and forming a III-V layer on the thin silicon layer, where the III-V layer is relaxed, the thin silicon layer is strained, and the porous silicon layer is partially strained.

Abstract: Methods for removing a material layer from a base substrate utilizing spalling in which mode III stress, i.e., the stress that is perpendicular to the fracture front created in the base substrate, during spalling is reduced. The substantial reduction of the mode III stress during spalling results in a spalling process in which the spalled material has less surface roughness at one of its' edges as compared to prior art spalling processes in which the mode III stress is present and competes with spalling.

Abstract: Techniques for integrating spalling into layer transfer processes involving optical device semiconductor materials are provided. In one aspect, a layer transfer method for an optical device semiconductor material includes forming the optical device semiconductor material on a first substrate; depositing a metal stressor layer on top of the optical device semiconductor material; attaching a first handle layer to the metal stressor layer; removing the optical device semiconductor material from the first substrate by pulling the first handle layer away from the first substrate; attaching a second handle layer to the optical device semiconductor material; removing the first handle layer from the stack; and forming a second substrate on the stressor layer. Vertical LED devices and techniques for formation thereof are also provided.

Abstract: A strain relaxed silicon germanium layer that has a low defect density is formed on a surface of a silicon substrate without causing wafer bowing. The strain relaxed silicon germanium layer is formed using multiple epitaxial growing, bonding and transferring steps. In the present application, a thick silicon germanium layer having a low defect density is grown on a transferred portion of a topmost silicon germanium sub-layer of an initial strain relaxed silicon germanium graded buffer layer and then bonded to a silicon substrate. A portion of the thick silicon germanium layer is then transferred to the silicon substrate. Additional steps of growing a thick silicon germanium layer having a low defect density, bonding and layer transfer may be performed as necessary.

Abstract: A method includes providing a semiconductor substrate having a plurality of linear semiconductor fin structures spaced apart from one another on a surface of the substrate; siliciding sidewalls of the semiconductor fin structures; removing an unsilicided central portion of each semiconductor fin structure leaving, for a given one of the semiconductor fin structures, a pair of silicide fin structures that are parallel to one another and spaced apart from one another by a distance about equal to a width of the removed unsilicided central portion of the semiconductor fin structure; and forming contacts to conductively connect together a plurality of the silicide fin structures to form a resistor. A resistance value of the resistor is related at least to a type of silicide, a number of contacted adjacent silicide fin structures and a length between two contacts.

Abstract: MIS capacitors are formed using a finned semiconductor structure. A highly doped region including the fins is formed within the structure and forms one plate of a MIS capacitor. A metal layer forms a second capacitor plate that is separated from the first plate by a high-k capacitor dielectric layer formed directly on the highly doped fins. Contacts are electrically connected to the capacitor plates. A highly doped implantation layer having a conductivity type opposite to that of the highly doped region provides electrical isolation within the structure.

Abstract: A method includes providing a semiconductor substrate having a plurality of linear semiconductor fin structures spaced apart from one another on a surface of the substrate; siliciding sidewalls of the semiconductor fin structures; removing an unsilicided central portion of each semiconductor fin structure leaving, for a given one of the semiconductor fin structures, a pair of silicide fin structures that are parallel to one another and spaced apart from one another by a distance about equal to a width of the removed unsilicided central portion of the semiconductor fin structure; and forming contacts to conductively connect together a plurality of the silicide fin structures to form a resistor. A resistance value of the resistor is related at least to a type of silicide, a number of contacted adjacent silicide fin structures and a length between two contacts.

Abstract: A method includes providing a semiconductor substrate having a plurality of linear semiconductor fin structures spaced apart from one another on a surface of the substrate; siliciding sidewalls of the semiconductor fin structures; removing an unsilicided central portion of each semiconductor fin structure leaving, for a given one of the semiconductor fin structures, a pair of silicide fin structures that are parallel to one another and spaced apart from one another by a distance about equal to a width of the removed unsilicided central portion of the semiconductor fin structure; and forming contacts to conductively connect together a plurality of the silicide fin structures to form a resistor. A resistance value of the resistor is related at least to a type of silicide, a number of contacted adjacent silicide fin structures and a length between two contacts.

Abstract: A photovoltaic device includes a substrate layer having a plurality of three-dimensional structures formed therein providing a textured profile. A first electrode is formed over the substrate layer and extends over the three-dimensional structures including non-planar surfaces. The first electrode has a thickness configured to maintain the textured profile, and the first electrode includes a transparent conductive material having a dopant metal activated within the transparent conductive material. A continuous photovoltaic stack is conformally formed over the first electrode, and a second electrode is formed on the photovoltaic stack.

Abstract: A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins. A surface of the porous fins is treated to make the surface suitable for epitaxial growth. Lattice mismatch is compensated for between an epitaxially grown monocrystalline layer grown on the surface and the monocrystalline substrate by relaxing the epitaxially grown monocrystalline layer using the porous fins to form a relaxed heteroepitaxial interface with the monocrystalline substrate.

Abstract: A method of forming a semiconductor device that includes providing regions of epitaxial oxide material on a substrate of a first lattice dimension, wherein regions of the epitaxial oxide material separate regions of epitaxial semiconductor material having a second lattice dimension are different than the first lattice dimension to provide regions of strained semiconductor. The regions of the strained semiconductor material are patterned to provide regions of strained fin structures. The epitaxial oxide that is present in the gate cut space obstructs relaxation of the strained fin structures. A gate structure is formed on a channel region of the strained fin structures separating source and drain regions of the fin structures.