Patents by Inventor Keith Jenkins

Keith Jenkins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180032939
    Abstract: A computer-implemented method for analyzing customer satisfaction is presented. The computer-implemented method may include capturing visual images related to individuals and order consumables, determining, by a processor, at least one measurable metric to predict variations indicating different satisfaction levels, and dynamically refining parameters if the variations exceed one or more thresholds. The computer-implemented method further includes receiving the captured visual images of the individuals and the order consumables by least one camera in communication with the processor.
    Type: Application
    Filed: July 27, 2016
    Publication date: February 1, 2018
    Inventors: Karthik Balakrishnan, Keith A. Jenkins, Barry P. Linder
  • Patent number: 9866221
    Abstract: Embodiments are directed to a system for synchronizing switching events. The system includes a controller, a clock generator communicatively coupled to the controller and a delay chain communicatively coupled to the controller. The delay chain is configured to perform a plurality of delay chain switching events in response to an input to the delay chain. The controller is configured to initiate a synchronization phase that includes enabling the clock generator to provide as an input to the delay chain a clock generator output at a synchronization frequency, wherein the clock generator output passing through the delay chain synchronizes the plurality of delay chain switching events to occur at the synchronization frequency resulting in a frequency of an output of the delay chain being synchronized to the synchronization frequency of the clock generator output.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: January 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith A. Jenkins, Barry P. Linder
  • Patent number: 9863994
    Abstract: Method of measuring semiconductor device leakage which includes: providing a semiconductor device powered by a supply voltage and having a circuit block of transistors; providing on the semiconductor device a test circuit providing an input to a counter and a fixed-frequency measurement clock to provide a clock signal to the counter; disconnecting a system clock from the circuit block; receiving by the test circuit the supply voltage as an input; initializing the counter; starting the counter when the supply voltage is at or below a first voltage Vhigh; monitoring a decrease of the supply voltage with time; stopping the counter when the supply voltage is at or below a second voltage Vlow such that Vhigh is greater than Vlow; and reading the counter to provide the semiconductor device leakage metric. Also disclosed is an apparatus and a computer program product.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: January 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Chen-Yong Cher, Keith A. Jenkins, Barry P. Linder
  • Publication number: 20170350928
    Abstract: Methods and systems for measuring a duty cycle of a signal include applying a first branch of an input signal directly to a latch. A delay of a second branch of the input signal is incrementally increased, with the second branch being applied to the latch, until the latch changes its output. A delay, corresponding to the latch's changed output, is divided by a period of the input signal to determine a duty cycle of the input signal.
    Type: Application
    Filed: August 23, 2017
    Publication date: December 7, 2017
    Inventor: Keith A. Jenkins
  • Patent number: 9835583
    Abstract: A method of assembling a remote sensor system to detect a gas or chemical and a remote sensor system are described. The method includes fabricating a sensor, the sensor outputting a sensor signal that changes upon contact of the sensor with the gas or chemical and the sensor having an input port for a clock signal, coupling a capacitor to the sensor, the capacitor output voltage resulting from the sensor signal output by the sensor, and coupling a mixer to the capacitor and a low frequency oscillator, the mixer configured to mix the capacitor output voltage with the low frequency oscillator output to generate an output signal. The method also includes coupling an antenna to the mixer, the antenna configured to transmit the output signal indicating detection of the gas or chemical.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: December 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shu-Jen Han, Keith A. Jenkins
  • Patent number: 9835584
    Abstract: A method of assembling a remote sensor system to detect a gas or chemical and a remote sensor system are described. The method includes fabricating a sensor, the sensor outputting a sensor signal that changes upon contact of the sensor with the gas or chemical and the sensor having an input port for a clock signal, coupling a capacitor to the sensor, the capacitor output voltage resulting from the sensor signal output by the sensor, and coupling a mixer to the capacitor and a low frequency oscillator, the mixer configured to mix the capacitor output voltage with the low frequency oscillator output to generate an output signal. The method also includes coupling an antenna to the mixer, the antenna configured to transmit the output signal indicating detection of the gas or chemical.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: December 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shu-Jen Han, Keith A. Jenkins
  • Publication number: 20170346492
    Abstract: Embodiments are directed to a system for synchronizing switching events. The system includes a controller, a clock generator communicatively coupled to the controller and a delay chain communicatively coupled to the controller. The delay chain is configured to perform a plurality of delay chain switching events in response to an input to the delay chain. The controller is configured to initiate a synchronization phase that includes enabling the clock generator to provide as an input to the delay chain a clock generator output at a synchronization frequency, wherein the clock generator output passing through the delay chain synchronizes the plurality of delay chain switching events to occur at the synchronization frequency resulting in a frequency of an output of the delay chain being synchronized to the synchronization frequency of the clock generator output.
    Type: Application
    Filed: May 24, 2016
    Publication date: November 30, 2017
    Inventors: Keith A. Jenkins, Barry P. Linder
  • Patent number: 9829535
    Abstract: An integrated circuit includes a test block which in turn includes a plurality of identical paths; a counter selectively coupled to the plurality of identical paths to selectively obtain a count of at least one of correctly operating paths and incorrectly operating paths from each of the plurality of identical paths; and a plurality of count latches selectively coupled to the counter to store output of the counter. Each path in turn includes a first clocked latch; a clocked logic path beginning and ending at the first clocked latch; and a clocked detection circuit coupled to the first clocked latch and the counter, which determines whether the clocked logic path is operating properly in a given clock period.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: November 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Bruce M. Fleischer, Keith A. Jenkins, Christos Vezyrtzis
  • Publication number: 20170339167
    Abstract: A software signature transceiver includes a signature receiver configured to couple to a programmable electronic device and sense a signature signal generated by the programmable electronic device, wherein the signature signal varies according to computer program codes executed by the programmable electronic device, and a signature transmitter operably connected to the signature receiver, the signature transmitter configured to transmit a signature transmission signal corresponding to the signature signal. A corresponding method to use the software signature transceiver and a software monitoring device to determine whether unknown software is executing on a programmable electronic device is also disclosed herein. A corresponding system comprising the programmable electronic device, the software signature transceiver, and a software monitoring device is also disclosed herein.
    Type: Application
    Filed: May 20, 2016
    Publication date: November 23, 2017
    Inventors: Keith A. Jenkins, Raphael P. Robertazzi, Alberto Valdes Garcia
  • Publication number: 20170329685
    Abstract: A method and system are provided for chip testing. The method includes ascertaining a baseline for a functioning chip with no stress history by performing a non-destructive test procedure on the functioning chip. The method further includes repeating the test procedure on a chip under test using a threshold derived from the baseline as a reference point to determine a stress history of the chip under test. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto, ranking each pattern based on at least one preceding available pattern to provide a plurality of pattern ranks, and calculating a sum by summing the pattern ranks. The sum calculated by the ascertaining step is designated as the baseline, and the sum calculated by the repeating step is compared to the threshold to determine the stress history of the chip under test.
    Type: Application
    Filed: May 16, 2016
    Publication date: November 16, 2017
    Inventors: Keith A. Jenkins, Barry P. Linder, Emily A. Ray, Raphael P. Robertazzi, Peilin Song, James H. Stathis, Kevin G. Stawiasz, Franco Stellari, Alan J. Weger, Emmanuel Yashchin
  • Patent number: 9817047
    Abstract: Methods and systems for measuring a duty cycle of a signal include applying a first branch of an input signal directly to a latch. A delay of a second branch of the input signal is incrementally increased, with the second branch being applied to the latch, until the latch changes its output. A delay, corresponding to the latch's changed output, is divided by a period of the input signal to determine a duty cycle of the input signal.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Corporation
    Inventor: Keith A. Jenkins
  • Publication number: 20170325093
    Abstract: A method for gaining access beyond a restricted access gateway includes an access key sequence stored on memory of a device. The access key sequence includes a sequence of key entries and key touch movements. An entered request sequence including keys activated by touch on a keyboard of the device and directions of touch movements made on the keyboard is recorded. With an access controller, it is determined whether the recorded entered request sequence matches the access key sequence. Access beyond the restricted access gateway is granted to functions when the recorded entered request sequence matches the access key sequence.
    Type: Application
    Filed: May 3, 2016
    Publication date: November 9, 2017
    Inventors: Keith A. Jenkins, Barry P. Linder
  • Publication number: 20170310277
    Abstract: A voltage controlled oscillator (VCO) and a method of operating the VCO are disclosed. The VCO includes an inductor device, a capacitor device coupled in parallel with the inductor device through first and second nodes, and a pair of cross-coupled transistors coupled in parallel with the inductor device and the capacitor device through the first and second nodes. At least one of the pair of cross-coupled transistor includes a plurality of sub transistors coupled in parallel. The sub transistors are individually switchable to adjust current drive capability of each of the sub transistors. Each of the sub transistors includes a first gate and a second gate.
    Type: Application
    Filed: April 20, 2016
    Publication date: October 26, 2017
    Inventors: Shu-Jen Han, Keith A. Jenkins
  • Patent number: 9791499
    Abstract: A test structure and method to detect open circuits due to electromigration or burn-out in test wires and inter-level vias. Electromigration occurs when current flows through circuit wires leading to a circuit interruption within the wire. The test structure is a passive test wire arranged in one of several configurations within the circuit of a computer chip. The dimensions and resistances of test wires can vary according to the test structure configuration. Each test wire is measured for an electrical discontinuity after the computer chip is powered-on. If a wiring interruption is detected, it is concluded that the chip had been powered-on before.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: October 17, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith A. Jenkins, Barry P. Linder, Kevin G. Stawiasz
  • Patent number: 9791500
    Abstract: A test structure and method to detect open circuits due to electromigration or burn-out in test wires and inter-level vias. Electromigration occurs when current flows through circuit wires leading to a circuit interruption within the wire. The test structure is a passive test wire arranged in one of several configurations within the circuit of a computer chip. The dimensions and resistances of test wires can vary according to the test structure configuration. Each test wire is measured for an electrical discontinuity after the computer chip is powered-on. If a wiring interruption is detected, it is concluded that the chip had been powered-on before.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: October 17, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith A. Jenkins, Barry P. Linder, Kevin G. Stawiasz
  • Patent number: 9787473
    Abstract: Techniques for use of carbon nanotubes as an anti-tampering feature and for use of randomly metallic or semiconducting carbon nanotubes in the generation of a physically unclonable cryptographic key generation are provided. In one aspect, a cryptographic key having an anti-tampering feature is provided which includes: an array of memory bits oriented along at least one bit line and at least one word line, wherein each of the memory bits comprises a memory cell, wherein the cryptographic key is stored in the memory cell, and wherein the memory cell is connected to the at least one bit line; and a metallic carbon nanotube interconnect which connects the memory cell to the at least one word line. A cryptographic key and method for processing the cryptographic key are also provided.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Wilfried Haensch, Shu-Jen Han, Keith A. Jenkins, Dirk Pfeiffer
  • Publication number: 20170276728
    Abstract: Embodiments are directed to a system for measuring a degradation characteristic of a plurality of electronic components. The system includes a parallel stress generator communicatively coupled to the plurality of electronic components, and a serial electronic measuring component communicatively coupled to the plurality of electronic components. The parallel stress generator is configured to generate a plurality of stress signals, apply the plurality of stress signals in parallel to the plurality of electronic components and remove the plurality of stress signals from the plurality of electronic components. The serial electronic measuring component is configured to, subsequent to the removal of the plurality of stress signals, sequentially measure the degradation characteristic of each one of the plurality of electronic components in order to determine their degradation resulting from the applied stress signals.
    Type: Application
    Filed: March 25, 2016
    Publication date: September 28, 2017
    Inventors: Keith A. Jenkins, Barry P. Linder
  • Publication number: 20170269152
    Abstract: Embodiments include methods, and systems of an integrated circuit having electromigration wearout detection circuits. Integrated circuit may include a detection element and a reference element. Detection element is subject to normal operation current. Reference element is not subject to normal operation current. A resistance of detection element is monitored to detect electromigration wearout. The electromigration wearout detection monitoring circuit may be configured to perform: periodically measuring resistance of detection element, calculating resistance change of detection element over a predetermined time period, comparing resistance change of detection element calculated to a predetermined safety threshold, and take mitigation actions when resistance change of detection element exceeds predetermined safety threshold. The mitigation actions may include switching to a redundant circuit of the integrated circuit, shutting down the integrated circuit, and sending a signal to initiate a service call.
    Type: Application
    Filed: March 15, 2016
    Publication date: September 21, 2017
    Inventors: Keith A. Jenkins, Siyuranga O. Koswatta
  • Publication number: 20170254846
    Abstract: Method of measuring semiconductor device leakage which includes: providing a semiconductor device powered by a supply voltage and having a circuit block of transistors; providing on the semiconductor device a test circuit providing an input to a counter and a fixed-frequency measurement clock to provide a clock signal to the counter; disconnecting a system clock from the circuit block; receiving by the test circuit the supply voltage as an input; initializing the counter; starting the counter when the supply voltage is at or below a first voltage Vhigh; monitoring a decrease of the supply voltage with time; stopping the counter when the supply voltage is at or below a second voltage Vlow such that Vhigh is greater than Vlow; and reading the counter to provide the semiconductor device leakage metric. Also disclosed is an apparatus and a computer program product.
    Type: Application
    Filed: March 3, 2016
    Publication date: September 7, 2017
    Inventors: Chen-Yong Cher, Keith A. Jenkins, Barry P. Linder
  • Patent number: 9746386
    Abstract: A strapping device for a pipe and methods of using the strapping device to non-invasively detect pressure inside the pipe and the residual stress exerted on the pipe. The strapping device includes a linked or a solid band adapted to be fitted around an outside diameter of the pipe. The strapping device further includes a sensor for measuring at least one of a change in the outside diameter of the pipe due to a corresponding change in pressure inside the pipe and to detect the stress or strain transferred from the pipe. The measurements can be conveniently processed in a circuit board coupled to the strapping device or in a remote location. The measurements can be transmitted through wires or digitally transmitted to the circuit board.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: August 29, 2017
    Assignee: ADVANCED SENSOR DESIGN TECHNOLOGIES, LLC
    Inventor: Keith Jenkins