Abstract: A structure includes a substrate which includes a surface. The structure also includes a horizontal-type Hall sensor positioned within the substrate and below the surface of the substrate. The structure further includes a protective overcoat layer positioned above the surface of the substrate, and a sphere-shaped magnetic concentrator positioned above the protective overcoat layer. Instead of or in addition to the sphere-shaped magnetic concentrator, the structure may include an embedded magnetic concentrator positioned within the substrate and below the horizontal-type Hall sensor.

Abstract: A structure includes a substrate which includes a surface. The structure also includes a horizontal-type Hall sensor positioned within the substrate and below the surface of the substrate. The structure further includes a patterned magnetic concentrator positioned above the surface of the substrate, and a protective overcoat layer positioned above the magnetic concentrator.

Abstract: A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.

Abstract: A Hall sensor includes a Hall well, such as an implanted region in a surface layer of a semiconductor structure, and four doped regions spaced apart from one another in the implanted region. The implanted region and the doped regions include majority carriers of the same conductivity type. The sensor also includes a dielectric layer that extends over the implanted region, and an electrode layer over the dielectric layer to operate as a control gate to set or adjust the sensor performance. A first supply circuit provides a first bias signal to a first pair of the terminals, and a second supply circuit provides a second bias signal to the electrode layer.

Abstract: A device having a first terminal region and a second terminal region. The first terminal region includes fine-tune (FT) metal stripes that are separated from each other by a first distance along the longitudinal direction. The second terminal region is spaced apart from the first terminal region by at least an inter-terminal distance. The second terminal region includes coarse-tune (CT) metal stripes that are separated from each other by a second distance along the longitudinal direction. The second distance is greater than the first distance, and the inter-terminal distance greater than the second distance. Each of the FT metal stripes may be selected as a first access location, and each of the CT metal stripes may be selected as a second access location. A pair of selected first and second access locations access a sheet resistance defined by a distance therebetween.

Abstract: A Hall effect sensor comprises a semiconductor substrate, a first well formed in the semiconductor substrate, a first ohmic contact formed in the first well, a second ohmic contact formed in the first well, a first terminal electrically coupled to the first ohmic contact, a second terminal electrically coupled to the second ohmic contact, and a first metal layer formed over the semiconductor substrate. The first metal layer comprises a first interconnect and a first trace, where the first trace is formed over the first well, and where the first interconnect electrically couples a first part of the first well to a second part of the first well. The first and second ohmic contacts are each positioned between the first part and the second part of the first well, where the first interconnect is electrically isolated from the first trace.

Abstract: A device having a first terminal region and a second terminal region. The first terminal region includes fine-tune (FT) metal stripes that are separated from each other by a first distance along the longitudinal direction. The second terminal region is spaced apart from the first terminal region by at least an inter-terminal distance. The second terminal region includes coarse-tune (CT) metal stripes that are separated from each other by a second distance along the longitudinal direction. The second distance is greater than the first distance, and the inter-terminal distance greater than the second distance. Each of the FT metal stripes may be selected as a first access location, and each of the CT metal stripes may be selected as a second access location. A pair of selected first and second access locations access a sheet resistance defined by a distance therebetween.

Abstract: Various examples provide an electronic device that includes first and second rectangular resistor segments, each resistor segment having a doped resistive region formed in a semiconductor substrate. The first resistor segment has a first trim end and a first bridge end, and the second resistor segment has a second bridge end. The first bridge end is adjacent the second bridge end. A conductive interconnect line connects to the first bridge end and to the second bridge end. At least one connection terminal to the first resistor segment is located at the first trim end.

Abstract: A vertical Hall element and method of fabricating are disclosed. The method includes forming a buried region having a first conductivity type in a substrate having a second conductivity type and implanting a dopant of the first conductivity type into a well region between the top surface of the substrate and the buried region. The buried region has a doping concentration increasing with an increasing depth from a top surface of the substrate and the well region has a doping concentration decreasing from the top surface of the substrate to the buried region. The method includes forming first through fifth contacts on the well region. First and second contacts define a conductive path and second and third contacts define another conductive path through the well region. The fourth contact is formed between first and second contacts and the fifth contact is formed between second and third contacts.

Abstract: A microelectronic device includes a vertical Hall sensor for measuring magnetic fields in two dimensions. In one implementation, the disclosed microelectronic device involves a vertical Hall plate with a cross-shaped upper terminal and a lower terminal which includes a buried layer. The cross-shaped upper terminal has a length-to-width ratio of 5 to 12 where it contacts the vertical Hall plate. The length is measured from one end of one arm of the cross-shaped upper terminal to an opposite end of an opposite arm. The width is an average width of both arms. Hall sense taps are located outside of the cross-shaped upper terminal. Current returns connect to the buried layer.

Abstract: A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.

Abstract: A Hall effect sensor comprises a semiconductor substrate, a first well formed in the semiconductor substrate, a first ohmic contact formed in the first well, a second ohmic contact formed in the first well, a first terminal electrically coupled to the first ohmic contact, a second terminal electrically coupled to the second ohmic contact, and a first metal layer formed over the semiconductor substrate. The first metal layer comprises a first interconnect and a first trace, where the first trace is formed over the first well, and where the first interconnect electrically couples a first part of the first well to a second part of the first well. The first and second ohmic contacts are each positioned between the first part and the second part of the first well, where the first interconnect is electrically isolated from the first trace.

Abstract: A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.

Abstract: Disclosed examples provide wafer-level integration of magnetoresistive sensors and Hall-effect sensors in a single integrated circuit, in which one or more vertical and/or horizontal Hall sensors are formed on or in a substrate along with transistors and other circuitry, and a magnetoresistive sensor circuit is formed in the IC metallization structure.

Abstract: Disclosed examples provide wafer-level integration of magnetoresistive sensors and Hall-effect sensors in a single integrated circuit, in which one or more vertical and/or horizontal Hall sensors are formed on or in a substrate along with transistors and other circuitry, and a magnetoresistive sensor circuit is formed in the IC metallization structure.

Abstract: A microelectronic device includes a vertical Hall sensor for measuring magnetic fields in two dimensions. In one implementation, the disclosed microelectronic device involves a vertical Hall plate with a cross-shaped upper terminal and a lower terminal which includes a buried layer. The cross-shaped upper terminal has a length-to-width ratio of 5 to 12 where it contacts the vertical Hall plate. The length is measured from one end of one arm of the cross-shaped upper terminal to an opposite end of an opposite arm. The width is an average width of both arms. Hall sense taps are located outside of the cross-shaped upper terminal. Current returns connect to the buried layer.

Abstract: Disclosed examples provide wafer-level integration of magnetoresistive sensors and Hall-effect sensors in a single integrated circuit, in which one or more vertical and/or horizontal Hall sensors are formed on or in a substrate along with transistors and other circuitry, and a magnetoresistive sensor circuit is formed in the IC metallization structure.

Abstract: A vertical Hall element and method of fabricating are disclosed. The method includes forming a buried region having a first conductivity type in a substrate having a second conductivity type and implanting a dopant of the first conductivity type into a well region between the top surface of the substrate and the buried region. The buried region has a doping concentration increasing with an increasing depth from a top surface of the substrate and the well region has a doping concentration decreasing from the top surface of the substrate to the buried region. The method includes forming first through fifth contacts on the well region. First and second contacts define a conductive path and second and third contacts define another conductive path through the well region. The fourth contact is formed between first and second contacts and the fifth contact is formed between second and third contacts.

Abstract: A device having a first terminal region and a second terminal region. The first terminal region includes fine-tune (FT) metal stripes that are separated from each other by a first distance along the longitudinal direction. The second terminal region is spaced apart from the first terminal region by at least an inter-terminal distance. The second terminal region includes coarse-tune (CT) metal stripes that are separated from each other by a second distance along the longitudinal direction. The second distance is greater than the first distance, and the inter-terminal distance greater than the second distance. Each of the FT metal stripes may be selected as a first access location, and each of the CT metal stripes may be selected as a second access location. A pair of selected first and second access locations access a sheet resistance defined by a distance therebetween.

Abstract: A vertical Hall element and method of fabricating are disclosed. The method includes forming a buried region having a first conductivity type in a substrate having a second conductivity type and implanting a dopant of the first conductivity type into a well region between the top surface of the substrate and the buried region. The buried region has a doping concentration increasing with an increasing depth from a top surface of the substrate and the well region has a doping concentration decreasing from the top surface of the substrate to the buried region. The method includes forming first through fifth contacts on the well region. First and second contacts define a conductive path and second and third contacts define another conductive path through the well region. The fourth contact is formed between first and second contacts and the fifth contact is formed between second and third contacts.