Patents by Inventor Keizo Kawakita

Keizo Kawakita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071425
    Abstract: Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include a first transmission line and a second transmission line located over one another. A via is shown connecting the first transmission line and a second transmission line wherein a first side of the via and a side of the second transmission line are coplanar. A via is also shown connecting the first transmission line and a second transmission line wherein the second transmission line tapers downward from a line width to a via width.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Hidenori Yamaguchi, Keizo Kawakita
  • Publication number: 20240071972
    Abstract: Apparatus and methods are disclosed, including stacked die devices and systems. Example stacked die devices and methods include an array of interconnect pillars that includes more than one pillar height. Example stacked die devices and methods include an array of interconnect pillars that includes a pillar height distribution mapped to a known warpage profile.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Hidenori Yamaguchi, Keizo Kawakita, Bang-Ning Hsu
  • Patent number: 11862554
    Abstract: Apparatuses and methods for controlling hydrogen supply in manufacturing memory devices are described. An example apparatus includes: a first capacitor disposed above a substrate; a hydrogen supply film above the first capacitor; a second capacitor above the hydrogen supply film; and a barrier film between the hydrogen supply film and the second capacitor. The hydrogen supply film provides hydrogen and/or hydrogen ions. The barrier film is hydrogen-impermeable.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: January 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Keizo Kawakita
  • Publication number: 20230377967
    Abstract: Disclosed herein is a method that includes: forming a mask layer on a semiconductor substrate; forming a photoresist on the mask layer; performing non-uniform exposure on the photoresist to provide a first patterned photoresist which includes a first region where the photoresist is removed to expose the mask layer and a second region where a part of the photoresist remains; first etching using the first patterned photoresist to remove the mask layer in the first region and form a first trench in the first region of the semiconductor substrate; second etching to provide a second patterned photoresist which includes the second region where the photoresist is removed; third etching using the second patterned photoresist to remove the mask layer in the second region; and fourth etching to deepen the first trench in the first region and form a second trench shallower than the first trench in the second region.
    Type: Application
    Filed: May 23, 2022
    Publication date: November 23, 2023
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Keizo Kawakita, Hidenori Yamaguchi
  • Patent number: 11810822
    Abstract: Apparatuses including structures in scribe lines are described. An example apparatus includes: a first chip and a second chip; a scribe region between the first chip and the second chip; a crack guide region in the scribe region, the crack guide region including a dicing line along which the first chip and the second chip are to be divided; and a structure disposed in the crack guide region and extending along the dicing line.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: November 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Keizo Kawakita, Raj K. Bansal, Tsung Che Tsai
  • Patent number: 11769736
    Abstract: Apparatuses and methods for manufacturing chips are described. An example method includes: forming at least one first dielectric layer above a substrate; forming at least one second dielectric layer above the first dielectric layer; forming a cover layer above the at least one second dielectric layer; forming a groove above the substrate by etching; covering at least an edge surface of the at least one first dielectric layer in the groove with a liner including polymer; forming a hole through the cover layer and a portion of the at least one second dielectric layer; depositing a conductive layer in the hole, on the cover layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: September 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hidenori Yamaguchi, Keizo Kawakita, Wataru Hoshino, Yuta Nomura
  • Patent number: 11764164
    Abstract: A semiconductor device includes a semiconductor substrate; and a multilevel wiring structure on the semiconductor substrate, the multilevel wiring structure including at least an intermediate metal layer over the semiconductor substrate and an uppermost metal layer over the intermediate metal layer, and the multilevel wiring structure being divided into a main circuit portion and a scribe portion surrounding the main circuit portion; wherein the scribe portion of the multilevel wiring layer includes at least a metal pad exposed in the intermediate metal layer.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Keizo Kawakita, Hidenori Yamaguchi, Bang Ning Hsu
  • Publication number: 20230290720
    Abstract: A semiconductor structure includes an opening formed in a surface of an insulating layer, and a lower metal layer on the surface of the insulating layer, and sidewalls and a bottom surface of the opening in the surface of the insulating layer. The sidewalls are tapered inwardly from the surface of the insulating layer to the bottom surface of the opening by a taper angle of between 10 degrees and 45 degrees.
    Type: Application
    Filed: March 10, 2022
    Publication date: September 14, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Hidenori Yamaguchi, Keizo Kawakita
  • Publication number: 20230187289
    Abstract: An apparatus includes an active region; a scribe region surrounding the active region; a test component in the scribe region; a pad electrode in the active region; and a power supply wiring of an upper wiring layer in the active region, the power supply wiring extending between the test component and the pad electrode; and an interconnection structure coupling the test component and the pad electrode across a border between the active region and the scribe region, the interconnection structure including a wiring portion of a lower wiring layer crossing the power supply wiring.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 15, 2023
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Haruka Momota, Koji Yasumori, Keizo Kawakita
  • Patent number: 11658121
    Abstract: A semiconductor device includes a semiconductor substrate; a first insulating film and a second insulating film provided above the semiconductor substrate; a low-k film provided between the first insulating film and the second insulating film; an element formation region in which elements included in an electric circuit are formed in the semiconductor substrate; a scribe region provided around the element formation region; a cut portion provided on the outer periphery of the scribe region; and a groove formed between the cut portion and the element formation region, wherein the groove penetrates through the low-k film.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: May 23, 2023
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Shigeru Sugioka, Hidenori Yamaguchi, Noriaki Fujiki, Keizo Kawakita
  • Patent number: 11637105
    Abstract: An apparatus comprising first and second interconnections spaced apart from one another, an interlayer insulating material over the first and second interconnections, first and second contacts in the interlayer insulating material and spaced apart from one another, third and fourth interconnections over the interlayer insulating material and spaced apart from one another, and compensation capacitors in a capacitor region. The third interconnections are coupled with the first interconnections through the first contacts and the fourth interconnections are coupled with the second interconnections through the second contacts. The compensation capacitors comprise lower electrodes over the interlayer insulating material, dielectric materials over the lower electrodes, and upper electrodes over the dielectric materials. The lower electrodes comprise edge portions in contact with the second contacts.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: April 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Keizo Kawakita
  • Patent number: 11616028
    Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-? dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: March 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Shams U. Arifeen, Hyunsuk Chun, Sheng Wei Yang, Keizo Kawakita
  • Publication number: 20230090041
    Abstract: Apparatuses including structures in scribe lines are described. An example apparatus includes: a first chip and a second chip; a scribe region between the first chip and the second chip; a crack guide region in the scribe region, the crack guide region including a dicing line along which the first chip and the second chip are to be divided; and a structure disposed in the crack guide region and extending along the dicing line.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Applicant: Micron Technology, Inc.
    Inventors: SHIGERU SUGIOKA, KEIZO KAWAKITA, RAJ K. BANSAL, TSUNG CHE TSAI
  • Patent number: 11600578
    Abstract: Apparatuses and methods for manufacturing chips are described. An example method includes: removing a first portion of a cover layer and at least one dielectric layer under the first portion of the cover layer in a cut region between chips to form a groove, and forming a support structure including a second portion of the cover layer and the at least one dielectric layer under the second portion of the cover layer in the cut region; removing a third portion of the cover layer in one of the chips and a portion of the at least one dielectric layer under the third portion of the cover layer to form an hole on the first chip; depositing a conductive layer to cover the cover layer and the hole; forming a conductive pillar on the conductive layer in the hole; and removing the conductive layer on the cover layer and an edge surface of the hole.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: March 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hidenori Yamaguchi, Wataru Hoshino, Keizo Kawakita
  • Patent number: 11587870
    Abstract: An apparatus comprising a multilevel wiring structure comprising aluminum interconnections. The aluminum interconnections comprise a first portion, a second portion, and a third portion, where the second portion is between the first portion and the third portion. The third portion comprises a greater width in a lateral direction than a width in the lateral direction of the second portion. A memory device comprising a memory array comprising memory cells and a control logic component electrically connected to the memory array. At least one of the memory cells comprises a multilevel wiring structure comprising interconnect structures, where the interconnect structures comprise a first portion, a second portion adjacent to the first portion, and a third portion adjacent to the second portion. The third portion comprises a greater width in a lateral direction than a width in the lateral direction of the second portion. Related apparatus, memory devices, and methods are also disclosed.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: February 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Noriaki Fujiki, Keizo Kawakita, Takahisa Ishino
  • Publication number: 20230048311
    Abstract: Bond pads for semiconductor die assemblies, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes a first semiconductor die including a first bond pad on a first side of the first semiconductor die. The semiconductor die assembly further includes a second semiconductor die including a second bond pad on a second side of the second semiconductor die. The first bond pad is aligned and bonded to the second bond pad at a bonding interface between the first and second bond pads, and at least one of the first and second bond pads include a first metal and a second metal different than the first metal. Further, the first metal is located at the bonding interface and the second metal has a first thickness corresponding to at least one-fourth of a second thickness of the first or second bond pad.
    Type: Application
    Filed: February 7, 2022
    Publication date: February 16, 2023
    Inventors: Bharat Bhushan, Akshay N. Singh, Keizo Kawakita, Bret K. Street
  • Patent number: 11569089
    Abstract: A method including forming an insulating film over first, second, third and fourth regions of a semiconductor substrate; forming a polyimide film on the insulating film; and patterning the polyimide film with a lithography method using a photomask including at least a first region of a first transmittance rate, a second region of a second transmittance rate, a third region having a shading material, and a fourth region, wherein the first, second, third and fourth regions of the photomask correspond to the first, second, third and fourth regions of the semiconductor substrate, respectively.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: January 31, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hidenori Yamaguchi, Keizo Kawakita, Wataru Hoshino, Shigeru Sugioka, Toshiyuki Maenosono
  • Publication number: 20230011222
    Abstract: According to one or more embodiments, a method of manufacturing a semiconductor device including a plurality of main circuit regions arranged in a matrix and a scribe region provided between the main circuit regions is provided. The method includes: forming a first insulating film; forming a low-k film; forming a plurality of penetrating portions penetrating through the low-k film; and forming a second insulating film under low-coverage film-forming conditions to form cavities in the plurality of through-holes.
    Type: Application
    Filed: September 26, 2022
    Publication date: January 12, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Hidenori Yamaguchi, Noriaki Fujiki, Keizo Kawakita, Raj K. Bansal
  • Publication number: 20230005837
    Abstract: Apparatuses and methods for controlling hydrogen supply in manufacturing memory devices are described. An example apparatus includes: a first capacitor disposed above a substrate; a hydrogen supply film above the first capacitor; a second capacitor above the hydrogen supply film; and a barrier film between the hydrogen supply film and the second capacitor. The hydrogen supply film provides hydrogen and/or hydrogen ions. The barrier film is hydrogen-impermeable.
    Type: Application
    Filed: July 2, 2021
    Publication date: January 5, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Keizo Kawakita
  • Publication number: 20220344278
    Abstract: Apparatuses and methods for manufacturing chips are described. An example method includes: removing a first portion of a cover layer and at least one dielectric layer under the first portion of the cover layer in a cut region between chips to form a groove, and forming a support structure including a second portion of the cover layer and the at least one dielectric layer under the second portion of the cover layer in the cut region; removing a third portion of the cover layer in one of the chips and a portion of the at least one dielectric layer under the third portion of the cover layer to form an hole on the first chip; depositing a conductive layer to cover the cover layer and the hole; forming a conductive pillar on the conductive layer in the hole; and removing the conductive layer on the cover layer and an edge surface of the hole.
    Type: Application
    Filed: April 22, 2021
    Publication date: October 27, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Hidenori Yamaguchi, Wataru Hoshino, Keizo Kawakita