Abstract: A semiconductor storage device comprises a peripheral circuit region including a wiring layer having wiring patterns, a cavity formed in a non-wiring region between the wiring patterns of the wiring layer, and an insulating film forming at least a part of a wall defining the cavity, and a memory cell region.

Abstract: A semiconductor device includes active areas which are insulatedly separated from each other by element-separation insulating films; a gate insulating film formed on each active area; a gate electrode which extends across the active area via the gate insulating film; a source area and a drain area formed in the active area so as to interpose the gate electrode; and a fin-channel structure in which at the intersection between the active area and the gate electrode, trenches are provided at both sides of the active area, and part of the gate electrode is embedded in each trench via the gate insulating film, so that the gate electrode extends across a fin which rises between the trenches. In the gate insulating film, the film thickness of a part which contacts the bottom surface of each trench is larger than that of a part which contacts the upper surface of the fin.

Abstract: A process for manufacturing a semiconductor device includes: forming first contact holes in a dielectric film for a PMOS transistor; depositing germanium on the source/drain regions of the PMOS transistor exposed from the first contact holes; heat treating the germanium with silicon in the source/drain regions of the PMOS transistor to form a germanium silicide film; forming second contact holes in the dielectric film for the source/drain regions of the NMOS transistor; and forming contact plugs in the first and second contact holes.

Abstract: A semiconductor storage device that is capable of utilizing dummy cells effectively and enhancing the memory cell density. Every second row of bit lines (second bit lines) in terminal memory mats 101A, 101C is not connected to first sense amplifiers SA1. Second sense amplifiers SA2 are arranged on the outside of the terminal memory mats, and second bit lines are connected according to a folded bit line system to the second sense amplifiers SA2. Two memory cells provided at the points where a word line WL intersects with a pair of bit lines BL, /BL connected to the second sense amplifiers SA2 constitute a twin cell unit TWC for storing a single bit of data in complementary fashion.

Abstract: The semiconductor device according to the present invention is a Fin-FET that can substantially increase the channel width without unnecessarily elevating the height of the Fin. The Fin-FET has gate electrodes 22 formed on the upper surface, both left and right sides and the bottom surface of channel-forming semiconductor layer 11a formed by processing semiconductor substrate 11 into a fin shape; and a channel region the four surfaces of which are surrounded by gate electrodes 22.

Abstract: A semiconductor device includes active areas which are insulatedly separated from each other by element-separation insulating films; a gate insulating film formed on each active area; a gate electrode which extends across the active area via the gate insulating film; a source area and a drain area formed in the active area so as to interpose the gate electrode; and a fin-channel structure in which at the intersection between the active area and the gate electrode, trenches are provided at both sides of the active area, and part of the gate electrode is embedded in each trench via the gate insulating film, so that the gate electrode extends across a fin which rises between the trenches. In the gate insulating film, the film thickness of a part which contacts the bottom surface of each trench is larger than that of a part which contacts the upper surface of the fin.

Abstract: A fabrication method for a wiring structure of the present invention includes: a process of forming a conductive wiring layer; a process of forming a wiring pattern on the wiring layer; a process of forming an insulative wiring interlayer film between wires of the wiring pattern; and a process of forming a plurality of longitudinal hole-shaped fine pores in the wiring interlayer film in a thickness direction of the wiring interlayer film by etching with a mask including one of nano-particles and material including nano-particles.

Abstract: This semiconductor device has an MOS transistor equipped with a gate electrode formed on a semiconductor substrate, a source region next to one side of the gate electrode, and a drain region next to another side of the gate electrode, wherein an upper end of the source region and an upper end of the drain region are at positions where are higher than a top surface of the semiconductor substrate, and the height of the upper end of the drain region differs from the height of the upper end of the source region.

Abstract: A FinFET includes a silicon layer deposited on a silicon substrate and configuring source/drain regions and a channel region. The gate of the FinFET includes a pair of first electrode layers sandwiching therebetween the channel region in the horizontal direction with an intervention of first gate insulation films, and a second gate electrode layer overlying the channel region with an intervention of a second gate insulation film and formed in contact with top of the first electrode layers.

Abstract: After forming a fin portion to be active region, openings are formed at portions corresponding to channel portions in a gate dielectric film 22 and a silicon nitride film 23 which cover the fin portion. Exposed surfaces of the silicon substrate 21 in the openings are oxidized to form oxide films 28. Then the oxide films 28 are removed. Hereby, the potions to be the channel portions of the fin portion are selectively reduced in width.

Abstract: A semiconductor device in which the concentration of the electric field at upper end portions (corner portions) of a fin-shaped active region is eased and deterioration of the threshold voltage of the FinFET is suppressed, and that has a high current driving performance, and a manufacturing method thereof are provided. The semiconductor device comprising: a fin-shaped active region having a top surface and side surfaces; a gate electrode covering the active region; a first gate insulating film formed between the top surface of the active region and the gate electrode; and a second gate insulating film formed between the side surfaces of the active region and the gate electrode, wherein the first gate insulating film is thicker than the second gate insulating film, and a dielectric constant of the first gate insulating film is higher than that of the second gate insulating film.

Abstract: In a MOS transistor having a structure in which a source and a drain are raised on a substrate by using a selective epitaxial growth technique, a bulk resistance can be reduced while an impurity concentration of a silicon layer is reduced in the selective epitaxial growth. A metal oxide semiconductor transistor includes a gate having a sidewall formed on a silicon substrate, a silicon layer formed on the silicon substrate by selective epitaxial growth, and an inclination portion inclined downward in a direction opposite to the gate on at least a portion of a cross-section including the silicon layer and the gate.

Abstract: A process for manufacturing a semiconductor device includes: forming first contact holes in a dielectric film for a PMOS transistor; depositing germanium on the source/drain regions of the PMOS transistor exposed from the first contact holes; heat treating the germanium with silicon in the source/drain regions of the PMOS transistor to form a germanium silicide film; forming second contact holes in the dielectric film for the source/drain regions of the NMOS transistor; and forming contact plugs in the first and second contact holes.

Abstract: A semiconductor device including a polysilicon plug with a reduced contact resistance and a manufacturing process therefor. The process includes the steps of forming a hole in an insulating layer on a semiconductor substrate; forming polysilicon over the whole surface of the insulating layer such that it fills the hole; forming a polysilicon plug in the hole by etching back a polysilicon; and heating the semiconductor substrate including the polysilicon plug within the insulating layer under a hydrogen atmosphere.

Abstract: A method of forming a semiconductor device is provided. A device isolation region is formed in a semiconductor substrate, thereby defining a device region in the semiconductor substrate. The device region has a flat main surface. The flat main surface is deformed into a round surface, thereby forming a surface-rounded device region. The surface-rounded device region includes a side portion that is adjacent to a boundary with the device isolation region. The surface-rounded device region has a convex shape in vertical cross section. An epitaxial layer is selectively formed on the round surface of the surface-rounded device region. A first ion-implantation process is carried out for introducing an impurity into at least one of the epitaxial layer and the surface-rounded device region.

Abstract: A semiconductor storage device that is capable of utilizing dummy cells effectively and enhancing the memory cell density. Every second row of bit lines (second bit lines) in terminal memory mats 101A, 101C is not connected to first sense amplifiers SA1. Second sense amplifiers SA2 are arranged on the outside of the terminal memory mats, and second bit lines are connected according to a folded bit line system to the second sense amplifiers SA2. Two memory cells provided at the points where a word line WL intersects with a pair of bit lines BL, /BL connected to the second sense amplifiers SA2 constitute a twin cell unit TWC for storing a single bit of data in complementary fashion.

Abstract: Improved open bit line architecture is disclosed, comprising two types of memory cell groups, which are different in size from each other. Normal memory mats are arranged in a predetermined direction and each comprises smaller sized memory cells such as 6F2 cells. Two end memory mats are arranged to sandwich the normal memory mats in the predetermined direction and comprises larger sized memory cells such as 8F2 cells. With the architecture, some advantages of folded bit line structure are introduced into open bit line structure.

Abstract: The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

Abstract: After a gate electrode made of a material containing a refractory metal is formed, the gate electrode is oxidized to form an oxide film for covering an exposed side surface of the gate electrode, at a predetermined temperature in an initial oxidization phase, and thereafter, the gate electrode is oxidized at a temperature higher than the predetermined temperature in an additional oxidization phase. Since the side surface of the gate electrode is covered with the oxide film in the initial oxidization phase, the refractory metal is prevented from being scattered from the side surface of the gate electrode in the additional oxidization phase. The layer resistance of the film containing the refractory metal is reduced because the additional oxidization phase is performed at the higher temperature.

Abstract: An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width.