Patents by Inventor Keizo Kinoshita

Keizo Kinoshita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200132951
    Abstract: An optical device includes a light-emitting element; an electronic circuit chip; a substrate on which the light-emitting element and the electronic circuit chip are mounted; a first electrode formed on a first mounting surface of the light-emitting element on the substrate; and a second electrode formed on a second mounting surface of the electronic circuit chip on the substrate. The first electrode and the second electrode have the same structure.
    Type: Application
    Filed: October 21, 2019
    Publication date: April 30, 2020
    Applicants: FUJITSU LIMITED, NEC Corporation, Photonics Electronics Technology Research Association
    Inventors: Nobuaki HATORI, Keizo KINOSHITA
  • Patent number: 10340399
    Abstract: Provided is an optical device in which an Si cap layer is provided on a Ge layer, and which is capable of effectively reducing dark current, while having a good effect on prevention of production line contamination by Ge. One embodiment of the optical device according to the present invention is provided with: a semiconductor layer which contains Ge and has a (001) surface and a facet surface between the (001) surface and a (110) surface; and a cap layer which is formed from Si, and which is formed on the (001) surface and the facet surface of the semiconductor layer. The ratio of the film thickness of the cap layer on the facet surface to the film thickness of the cap layer on the (001) surface is 0.4 or more; and the film thickness of the cap layer on the (001) surface is from 9 nm to 30 nm (inclusive).
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: July 2, 2019
    Assignee: PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Shigekazu Okumura, Tohru Mogami, Keizo Kinoshita, Tsuyoshi Horikawa, Junichi Fujikata
  • Patent number: 10247882
    Abstract: Provided is an optical waveguide circuit avoiding the difficulty of the property compensation based on temperature control, compensated with respect to the property variations due to fabrication error, particularly paid attention in a silicon waveguide, and being low in power consumption and high in performances. The optical waveguide circuit includes a silicon (Si) substrate, a buried oxide film (BOX) layer formed on the Si substrate, and an SOI (Silicon on Insulator) layer, formed on the BOX layer, including an optical element utilizing the SOI layer as a main optical transmission medium. At least part of a waveguide of the optical element includes uniformly distributed and thermally unstable crystal defects.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 2, 2019
    Assignees: NEC CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Tsuyoshi Horikawa, Tohru Mogami, Keizo Kinoshita
  • Publication number: 20190006532
    Abstract: Provided is an optical device in which an Si cap layer is provided on a Ge layer, and which is capable of effectively reducing dark current, while having a good effect on prevention of production line contamination by Ge. One embodiment of the optical device according to the present invention is provided with: a semiconductor layer which contains Ge and has a (001) surface and a facet surface between the (001) surface and a (110) surface; and a cap layer which is formed from Si, and which is formed on the (001) surface and the facet surface of the semiconductor layer. The ratio of the film thickness of the cap layer on the facet surface to the film thickness of the cap layer on the (001) surface is 0.4 or more; and the film thickness of the cap layer on the (001) surface is from 9 nm to 30 nm (inclusive).
    Type: Application
    Filed: July 28, 2016
    Publication date: January 3, 2019
    Applicant: PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Shigekazu Okumura, Tohru Mogami, Keizo Kinoshita, Tsuyoshi Horikawa, Junichi Fujikata
  • Patent number: 10162110
    Abstract: A semiconductor device is provided with an insulating layer formed on a base substrate, an optical waveguide composed of a semiconductor layer formed on the insulating layer, and an insulating film formed along an upper surface of the insulating layer and a front surface of the optical waveguide. A peripheral edge portion of a lower surface of the optical waveguide is separated from the insulating layer, and the insulating film is buried between the peripheral edge portion and the insulating layer.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: December 25, 2018
    Assignees: RENESAS ELECTRONICS CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Tatsuya Usami, Keiji Sakamoto, Yoshiaki Yamamoto, Shinichi Watanuki, Masaru Wakabayashi, Tohru Mogami, Tsuyoshi Horikawa, Keizo Kinoshita
  • Patent number: 10078182
    Abstract: When an optical waveguide is formed, an area of an opening of a resist mask is equal to an area of a semiconductor layer for a dummy pattern exposed from the resist mask, and the semiconductor layer for the dummy pattern exposed from the resist mask has a uniform thickness in a region in which the dummy pattern is formed. As a result, an effective pattern density does not change in etching the semiconductor layer for the dummy pattern, and accordingly, it is possible to form a rib-shaped optical waveguide having desired dimensions and a desired shape.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: September 18, 2018
    Assignees: RENESAS ELECTRONICS CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Shinichi Watanuki, Akira Mitsuiki, Atsuro Inada, Tohru Mogami, Tsuyoshi Horikawa, Keizo Kinoshita
  • Patent number: 9985149
    Abstract: A performance of a semiconductor device is improved. In a method of manufacturing a semiconductor device, a first semiconductor portion and a second semiconductor portion made of silicon are formed on a base body via an insulation layer, and a third semiconductor portion including a semiconductor layer made of germanium is formed on the second semiconductor portion. Next, an insulation film is formed above the first semiconductor portion, an opening portion reaching the first semiconductor portion from an upper surface of the insulation film is formed, and a metal silicide layer is formed on a part of an upper surface of the first semiconductor portion exposed to the opening portion.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: May 29, 2018
    Assignees: RENESAS ELECTRONICS CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto, Tohru Mogami, Tsuyoshi Horikawa, Keizo Kinoshita
  • Publication number: 20180067260
    Abstract: Provided is an optical waveguide circuit avoiding the difficulty of the property compensation based on temperature control, compensated with respect to the property variations due to fabrication error, particularly paid attention in a silicon waveguide, and being low in power consumption and high in performances. The optical waveguide circuit includes a silicon (Si) substrate, a buried oxide film (BOX) layer formed on the Si substrate, and an SOI (Silicon on Insulator) layer, formed on the BOX layer, including an optical element utilizing the SOI layer as a main optical transmission medium. At least part of a waveguide of the optical element includes uniformly distributed and thermally unstable crystal defects.
    Type: Application
    Filed: August 31, 2017
    Publication date: March 8, 2018
    Inventors: Tsuyoshi HORIKAWA, Tohru MOGAMI, Keizo KINOSHITA
  • Publication number: 20170069769
    Abstract: A performance of a semiconductor device is improved. In a method of manufacturing a semiconductor device, a first semiconductor portion and a second semiconductor portion made of silicon are formed on a base body via an insulation layer, and a third semiconductor portion including a semiconductor layer made of germanium is formed on the second semiconductor portion. Next, an insulation film is formed above the first semiconductor portion, an opening portion reaching the first semiconductor portion from an upper surface of the insulation film is formed, and a metal silicide layer is formed on a part of an upper surface of the first semiconductor portion exposed to the opening portion.
    Type: Application
    Filed: August 23, 2016
    Publication date: March 9, 2017
    Inventors: Tatsuya USAMI, Yoshiaki YAMAMOTO, Keiji SAKAMOTO, Tohru MOGAMI, Tsuyoshi HORIKAWA, Keizo KINOSHITA
  • Publication number: 20170068047
    Abstract: A semiconductor device is provided with an insulating layer formed on a base substrate, an optical waveguide composed of a semiconductor layer formed on the insulating layer, and an insulating film formed along an upper surface of the insulating layer and a front surface of the optical waveguide. A peripheral edge portion of a lower surface of the optical waveguide is separated from the insulating layer, and the insulating film is buried between the peripheral edge portion and the insulating layer.
    Type: Application
    Filed: August 22, 2016
    Publication date: March 9, 2017
    Inventors: TATSUYA USAMI, KEIJI SAKAMOTO, YOSHIAKI YAMAMOTO, SHINICHI WATANUKI, MASARU WAKABAYASHI, TOHRU MOGAMI, TSUYOSHI HORIKAWA, KEIZO KINOSHITA
  • Publication number: 20170068051
    Abstract: When an optical waveguide is formed, an area of an opening of a resist mask is equal to an area of a semiconductor layer for a dummy pattern exposed from the resist mask, and the semiconductor layer for the dummy pattern exposed from the resist mask has a uniform thickness in a region in which the dummy pattern is formed. As a result, an effective pattern density does not change in etching the semiconductor layer for the dummy pattern, and accordingly, it is possible to form a rib-shaped optical waveguide having desired dimensions and a desired shape.
    Type: Application
    Filed: August 22, 2016
    Publication date: March 9, 2017
    Inventors: Shinichi WATANUKI, Akira MITSUIKl, Atsuro INADA, Tohru MOGAMI, Tsuyoshi HORIKAWA, Keizo KINOSHITA
  • Patent number: 9406869
    Abstract: A semiconductor device includes: a first magnetic layer (1) disposed on a flat substrate surface; a second magnetic layer (3) disposed above the first magnetic layer (1) and magnetically coupled to the first magnetic layer (1) by magnetostatic coupling or exchange coupling; and a third thin film layer (8) formed between the first magnetic layer (1) and the second magnetic layer (3), the third thin film layer (8) having such a thickness as to avoid inhibiting the magnetic coupling between the first magnetic layer (1) and the second magnetic layer (3).
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: August 2, 2016
    Assignees: NEC CORPORATION, TOHOKU UNIVERSITY
    Inventors: Hiroaki Honjou, Keizo Kinoshita, Hideo Ohno
  • Publication number: 20150200354
    Abstract: A semiconductor device includes: a first magnetic layer (1) disposed on a flat substrate surface; a second magnetic layer (3) disposed above the first magnetic layer (1) and magnetically coupled to the first magnetic layer (1) by magnetostatic coupling or exchange coupling; and a third thin film layer (8) formed between the first magnetic layer (1) and the second magnetic layer (3), the third thin film layer (8) having such a thickness as to avoid inhibiting the magnetic coupling between the first magnetic layer (1) and the second magnetic layer (3).
    Type: Application
    Filed: April 24, 2013
    Publication date: July 16, 2015
    Applicants: TOHOKU UNIVERSITY, NEC CORPORATION
    Inventors: Hiroaki Honjou, Keizo Kinoshita, Hideo Ohno
  • Patent number: 8105661
    Abstract: A method of forming a porous film on a processing target includes: forming fine organic particles by polymerizing an organic compound in a gaseous phase; mixing the fine organic particles with a silicon compound containing a Si—O bond in a gaseous phase, thereby depositing a film containing the fine particles on the processing target; and removing the fine organic particles from the film.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: January 31, 2012
    Assignees: ASM Japan K.K., Ulvac, Inc., NEC Corporation
    Inventors: Yasuyoshi Hyodo, Kazuo Kohmura, Nobutoshi Fujii, Nobutaka Kunimi, Keizo Kinoshita
  • Publication number: 20110092071
    Abstract: Provided is a method for the effective silylation treatment of a silica-based porous insulating film having a plurality of pores. The method of producing a silylated porous insulating film (204c) includes a process whereby a porous insulating film (204b) having a plurality of pores is formed, and a process wherein a silylating material vapor (210) obtained by vaporizing silylating material containing organic silane compound having a hydrophobic group and polymerization inhibitor which inhibits the auto-polymerization of the organic silane compound is caused to act upon the porous insulating film (204b).
    Type: Application
    Filed: May 26, 2009
    Publication date: April 21, 2011
    Applicants: RENESAS ELECTRONICS CORPORATION, ULVAC INC.
    Inventors: Keizo Kinoshita, Shinichi Chikaki, Takahiro Nakayama
  • Patent number: 7585789
    Abstract: A method of forming a porous film on a semiconductor substrate includes: supplying a silicon compound containing at least one Si—O bond in its molecule in a gaseous phase into a reaction chamber; forming a siloxane oligomer through plasma reaction of the silicon compound; and supplying an organic amine in a gaseous phase into the reaction chamber and reacting the organic amine with the siloxane oligomer, thereby forming a porous film on the semiconductor substrate.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: September 8, 2009
    Assignees: ASM Japan K.K., Ulvac, Inc., NEC Corporation
    Inventors: Yasuyoshi Hyodo, Kazuo Kohmura, Nobutoshi Fujii, Nobutaka Kunimi, Keizo Kinoshita
  • Patent number: 7524908
    Abstract: A copolymerized high polymer film includes plural organic polymers, as skeleton, and is manufactured by blowing more than two kinds of organic monomers of respectively specific structures, in a vapor phase condition, onto the surface of a heated substrate, through plasma being generated in a reaction chamber. As a result, manufacture of an organic high polymer film capable of further reducing the effective relative permittivity of organic polymer films as a whole can be achieved, and, at the same time, further improvement in mechanical strength of film as well as film forming speed can be achieved.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: April 28, 2009
    Assignee: NEC Corporation
    Inventors: Jun Kawahara, Keizo Kinoshita, Nobutaka Kunimi, Akinori Nakano
  • Patent number: 7439315
    Abstract: A copolymer film having a decreased dielectric constant which is produced by supplying at least two organic monomers as raw materials, forming a film of a copolymer comprising a backbone based on said at least two monomers on a surface of a substrate, and heating the copolymer film at a temperature higher than a temperature at which the copolymer film is formed.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: October 21, 2008
    Assignee: NEC Corporation
    Inventors: Nobutaka Kunimi, Jun Kawahara, Akinori Nakano, Keizo Kinoshita
  • Publication number: 20070158013
    Abstract: A method of forming a porous film on a semiconductor substrate includes: supplying a silicon compound containing at least one Si—O bond in its molecule in a gaseous phase into a reaction chamber; forming a siloxane oligomer through plasma reaction of the silicon compound; and supplying an organic amine in a gaseous phase into the reaction chamber and reacting the organic amine with the siloxane oligomer, thereby forming a porous film on the semiconductor substrate.
    Type: Application
    Filed: November 27, 2006
    Publication date: July 12, 2007
    Inventors: Yasuyoshi Hyodo, Kazuo Kohmura, Nobutoshi Fujii, Nobutaka Kunimi, Keizo Kinoshita
  • Publication number: 20070161257
    Abstract: A method of forming a porous film on a processing target includes: forming fine organic particles by polymerizing an organic compound in a gaseous phase; mixing the fine organic particles with a silicon compound containing a Si—O bond in a gaseous phase, thereby depositing a film containing the fine particles on the processing target; and removing the fine organic particles from the film.
    Type: Application
    Filed: November 14, 2006
    Publication date: July 12, 2007
    Applicants: ASM JAPAN K.K., ULVAC, INC., NEC CORPORATION
    Inventors: Yasuyoshi Hyodo, Kazuo Kohmura, Nobutoshi Fujii, Nobutaka Kunimi, Keizo Kinoshita