Patents by Inventor Kejia Wang

Kejia Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210068350
    Abstract: The present invention is directed to a small hand-held garden tool, for example a hedgetrimmer, having an electrically powered powerhead, and a detachable pole assembly. The powerhead can be used alone to cut nearby vegetation or in combination with a pole assembly to reach vegetation farther away. The powerhead has a separate handle and motor chamber, with the pole assembly being secured to the motor chamber. Actuation of the powerhead is controlled by a trigger on the handle. However, when connected to the pole assembly, actuation of the powerhead is controlled by a second trigger on the pole assembly.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 11, 2021
    Inventors: Mark CHOU, Bojun SHI, Kejia WANG, Xiubao LAN
  • Patent number: 10420287
    Abstract: The present invention is directed to a small hand-held garden tool, for example a hedgetrimmer, having an electrically powered powerhead, and a detachable pole assembly. The powerhead can be used alone to cut nearby vegetation or in combination with a pole assembly to reach vegetation farther away. The powerhead has a separate handle and motor chamber, with the pole assembly being secured to the motor chamber. Actuation of the powerhead is controlled by a trigger on the handle. However, when connected to the pole assembly, actuation of the powerhead is controlled by a second trigger on the pole assembly.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: September 24, 2019
    Assignee: Black & Decker, Inc.
    Inventors: Mark Chou, Bojun Shi, Kejia Wang, Xiubao Lan
  • Patent number: 10355086
    Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: July 16, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC., STMICROELECTRONICS, INC.
    Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
  • Patent number: 10256304
    Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: April 9, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., GLOBALFOUNDRIES, INC.
    Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
  • Publication number: 20180175202
    Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.
    Type: Application
    Filed: February 7, 2018
    Publication date: June 21, 2018
    Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
  • Patent number: 9935179
    Abstract: A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: April 3, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., STMICROELECTRONICS, INC.
    Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
  • Patent number: 9935201
    Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.
    Type: Grant
    Filed: January 2, 2017
    Date of Patent: April 3, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC., STMICROELECTRONICS, INC.
    Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
  • Patent number: 9917195
    Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: March 13, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC., STMICROELECTRONICS ,INC.
    Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
  • Publication number: 20170251608
    Abstract: The present invention is directed to a small hand-held garden tool, for example a hedgetrimmer, having an electrically powered powerhead, and a detachable pole assembly. The powerhead can be used alone to cut nearby vegetation or in combination with a pole assembly to reach vegetation farther away. The powerhead has a separate handle and motor chamber, with the pole assembly being secured to the motor chamber. Actuation of the powerhead is controlled by a trigger on the handle. However, when connected to the pole assembly, actuation of the powerhead is controlled by a second trigger on the pole assembly.
    Type: Application
    Filed: March 3, 2016
    Publication date: September 7, 2017
    Inventors: Mark CHOU, Bojun SHI, Kejia WANG, Xiubao LAN
  • Publication number: 20170200812
    Abstract: A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.
    Type: Application
    Filed: March 29, 2017
    Publication date: July 13, 2017
    Inventors: XIUYU CAI, QING LIU, KEJIA WANG, RUILONG XIE, CHUN-CHEN YEH
  • Patent number: 9660057
    Abstract: Methods and structures for forming a reduced resistance region of a finFET are described. According to some aspects, a dummy gate and first gate spacer may be formed above a fin comprising a first semiconductor composition. At least a portion of source and drain regions of the fin may be removed, and a second semiconductor composition may be formed in the source and drain regions in contact with the first semiconductor composition. A second gate spacer may be formed covering the first gate spacer. The methods may be used to form finFETs having reduced resistance at source and drain junctions.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: May 23, 2017
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation, GLOBALFOUNDRIES Inc.
    Inventors: Qing Liu, Ruilong Xie, Chun-chen Yeh, Xiuyu Cai, Kejia Wang
  • Patent number: 9653579
    Abstract: A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: May 16, 2017
    Assignees: STMicroelectronics, Inc., GLOBALFOUNDRIES Inc, International Business Machines Corporation
    Inventors: Qing Liu, Ruilong Xie, Xiuyu Cai, Chun-chen Yeh, Kejia Wang
  • Publication number: 20170110583
    Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about le18 to about le20 atoms/cm3 and contacting the epitaxial contacts.
    Type: Application
    Filed: January 2, 2017
    Publication date: April 20, 2017
    Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
  • Patent number: 9620505
    Abstract: A semiconductor device which includes: a substrate; a first set of fins above the substrate of a first semiconductor material; a second set of fins above the substrate and of a second semiconductor material different than the first semiconductor material; and an isolation region positioned between the first and second sets of fins, the isolation region having a nitride layer. The isolation region may be an isolation pillar or an isolation trench.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: April 11, 2017
    Assignees: International Business Machines Corporation, STMicroelectronics, Inc., GlobalFoundries Inc.
    Inventors: Qing Liu, Xiuyu Cai, Ruilong Xie, Chun-chen Yeh, Kejia Wang, Daniel Chanemougame
  • Publication number: 20170033197
    Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.
    Type: Application
    Filed: June 14, 2016
    Publication date: February 2, 2017
    Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
  • Publication number: 20170033221
    Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.
    Type: Application
    Filed: July 29, 2015
    Publication date: February 2, 2017
    Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
  • Publication number: 20160260741
    Abstract: In forming a finFET, a selective nitridation process is used during spacer formation on the gate to support a finer fin pitch than could be achieved using traditional spacer deposition processes. The spacer formation may also allow precise control over formation of source and drain junctions.
    Type: Application
    Filed: May 16, 2016
    Publication date: September 8, 2016
    Applicants: STMicroelectronics, Inc., International Business Machines Corporation, GlobalFoundries Inc
    Inventors: Qing Liu, Chun-Chen Yeh, Ruilong Xie, Xiuyu Cai, Kejia Wang
  • Patent number: 9437677
    Abstract: A semiconductor device includes a substrate, a nanowire, a first structure, and a second structure. The nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate, where the nanowire includes a layer on a surface of the nanowire, where the layer includes at least one of silicide and carbide, where the layer has a substantially uniform shape.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: September 6, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Dechao Guo, Zhengwen Li, Kejia Wang, Zhen Zhang, Yu Zhu
  • Publication number: 20160197072
    Abstract: A semiconductor device which includes: a substrate; a first set of fins above the substrate of a first semiconductor material; a second set of fins above the substrate and of a second semiconductor material different than the first semiconductor material; and an isolation region positioned between the first and second sets of fins, the isolation region having a nitride layer. The isolation region may be an isolation pillar or an isolation trench.
    Type: Application
    Filed: March 17, 2016
    Publication date: July 7, 2016
    Inventors: Qing Liu, Xiuyu Cai, Ruilong Xie, Chun-chen Yeh, Kejia Wang, Daniel Chanemougame
  • Patent number: 9318579
    Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate, and a gate overlying the semiconductor fins. The gate has a tapered outer surface. A first pair of sidewall spacers is formed adjacent the gate an exposed tapered outer surface is also defined. Portions of the gate are removed at the exposed tapered outer surface to define a recess. A second pair of sidewall spacers is formed covering the first pair of sidewall spacers and the recess. Source/drain regions are formed on the semiconductor fins.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: April 19, 2016
    Assignees: STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Liu, Ruilong Xie, Xiuyu Cai, Kejia Wang, Chun-chen Yeh