Patents by Inventor Kejia Wang
Kejia Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250136867Abstract: The present disclosure provides curable compositions comprising one or more of polymerizable liquid crystalline compounds or polymerizable polyesters with disrupted crystallinity, as well as polymeric materials formed from the curable compositions. Further provided herein are methods of producing the compositions and using the same for the fabrication of medical devices, such as orthodontic appliances.Type: ApplicationFiled: October 31, 2024Publication date: May 1, 2025Inventors: Kejia Yang, Michael Christopher Cole, Xiance Wang, Umesh Upendra Choudhary
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Patent number: 11604948Abstract: A cascaded machine learning inference system and method is disclosed. The cascaded system and method may be designed to be employed in resource restricted environments. The cascaded system and method may be applicable for applications that operate with limited power (e.g., a wearable smart watch). The cascaded system and method may employ two or more subsystems that are operable to classify an input signal provided by any number or types of sensors suitable for a given application. For instance, the sensors used may include gyroscopes, accelerometers, magnetometers, or barometric altimeters. The system and method may also be further split functionality across additional or new subsystems. By splitting operations and functionality across additional subsystems, the overall power consumption may further be reduced.Type: GrantFiled: March 27, 2020Date of Patent: March 14, 2023Assignee: Robert Bosch GmbHInventors: Rudolf Bichler, Thomas Rocznik, Kejia Wang, Christian Peters
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Publication number: 20210303936Abstract: A cascaded machine learning inference system and method is disclosed. The cascaded system and method may be designed to be employed in resource restricted environments. The cascaded system and method may be applicable for applications that operate with limited power (e.g., a wearable smart watch). The cascaded system and method may employ two or more subsystems that are operable to classify an input signal provided by any number or types of sensors suitable for a given application. For instance, the sensors used may include gyroscopes, accelerometers, magnetometers, or barometric altimeters. The system and method may also be further split functionality across additional or new subsystems. By splitting operations and functionality across additional subsystems, the overall power consumption may further be reduced.Type: ApplicationFiled: March 27, 2020Publication date: September 30, 2021Inventors: Rudolf BICHLER, Thomas ROCZNIK, Kejia WANG, Christian PETERS
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Publication number: 20210068350Abstract: The present invention is directed to a small hand-held garden tool, for example a hedgetrimmer, having an electrically powered powerhead, and a detachable pole assembly. The powerhead can be used alone to cut nearby vegetation or in combination with a pole assembly to reach vegetation farther away. The powerhead has a separate handle and motor chamber, with the pole assembly being secured to the motor chamber. Actuation of the powerhead is controlled by a trigger on the handle. However, when connected to the pole assembly, actuation of the powerhead is controlled by a second trigger on the pole assembly.Type: ApplicationFiled: August 28, 2019Publication date: March 11, 2021Inventors: Mark CHOU, Bojun SHI, Kejia WANG, Xiubao LAN
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Patent number: 10420287Abstract: The present invention is directed to a small hand-held garden tool, for example a hedgetrimmer, having an electrically powered powerhead, and a detachable pole assembly. The powerhead can be used alone to cut nearby vegetation or in combination with a pole assembly to reach vegetation farther away. The powerhead has a separate handle and motor chamber, with the pole assembly being secured to the motor chamber. Actuation of the powerhead is controlled by a trigger on the handle. However, when connected to the pole assembly, actuation of the powerhead is controlled by a second trigger on the pole assembly.Type: GrantFiled: March 3, 2016Date of Patent: September 24, 2019Assignee: Black & Decker, Inc.Inventors: Mark Chou, Bojun Shi, Kejia Wang, Xiubao Lan
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Patent number: 10355086Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.Type: GrantFiled: June 14, 2016Date of Patent: July 16, 2019Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC., STMICROELECTRONICS, INC.Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
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Patent number: 10256304Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.Type: GrantFiled: February 7, 2018Date of Patent: April 9, 2019Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., GLOBALFOUNDRIES, INC.Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
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Publication number: 20180175202Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.Type: ApplicationFiled: February 7, 2018Publication date: June 21, 2018Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
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Patent number: 9935201Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.Type: GrantFiled: January 2, 2017Date of Patent: April 3, 2018Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC., STMICROELECTRONICS, INC.Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
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Patent number: 9935179Abstract: A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.Type: GrantFiled: March 29, 2017Date of Patent: April 3, 2018Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., STMICROELECTRONICS, INC.Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
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Patent number: 9917195Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.Type: GrantFiled: July 29, 2015Date of Patent: March 13, 2018Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC., STMICROELECTRONICS ,INC.Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
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Publication number: 20170251608Abstract: The present invention is directed to a small hand-held garden tool, for example a hedgetrimmer, having an electrically powered powerhead, and a detachable pole assembly. The powerhead can be used alone to cut nearby vegetation or in combination with a pole assembly to reach vegetation farther away. The powerhead has a separate handle and motor chamber, with the pole assembly being secured to the motor chamber. Actuation of the powerhead is controlled by a trigger on the handle. However, when connected to the pole assembly, actuation of the powerhead is controlled by a second trigger on the pole assembly.Type: ApplicationFiled: March 3, 2016Publication date: September 7, 2017Inventors: Mark CHOU, Bojun SHI, Kejia WANG, Xiubao LAN
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Publication number: 20170200812Abstract: A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.Type: ApplicationFiled: March 29, 2017Publication date: July 13, 2017Inventors: XIUYU CAI, QING LIU, KEJIA WANG, RUILONG XIE, CHUN-CHEN YEH
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Patent number: 9660057Abstract: Methods and structures for forming a reduced resistance region of a finFET are described. According to some aspects, a dummy gate and first gate spacer may be formed above a fin comprising a first semiconductor composition. At least a portion of source and drain regions of the fin may be removed, and a second semiconductor composition may be formed in the source and drain regions in contact with the first semiconductor composition. A second gate spacer may be formed covering the first gate spacer. The methods may be used to form finFETs having reduced resistance at source and drain junctions.Type: GrantFiled: June 17, 2014Date of Patent: May 23, 2017Assignees: STMicroelectronics, Inc., International Business Machines Corporation, GLOBALFOUNDRIES Inc.Inventors: Qing Liu, Ruilong Xie, Chun-chen Yeh, Xiuyu Cai, Kejia Wang
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Patent number: 9653579Abstract: A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.Type: GrantFiled: May 19, 2014Date of Patent: May 16, 2017Assignees: STMicroelectronics, Inc., GLOBALFOUNDRIES Inc, International Business Machines CorporationInventors: Qing Liu, Ruilong Xie, Xiuyu Cai, Chun-chen Yeh, Kejia Wang
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Publication number: 20170110583Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about le18 to about le20 atoms/cm3 and contacting the epitaxial contacts.Type: ApplicationFiled: January 2, 2017Publication date: April 20, 2017Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
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Patent number: 9620505Abstract: A semiconductor device which includes: a substrate; a first set of fins above the substrate of a first semiconductor material; a second set of fins above the substrate and of a second semiconductor material different than the first semiconductor material; and an isolation region positioned between the first and second sets of fins, the isolation region having a nitride layer. The isolation region may be an isolation pillar or an isolation trench.Type: GrantFiled: March 17, 2016Date of Patent: April 11, 2017Assignees: International Business Machines Corporation, STMicroelectronics, Inc., GlobalFoundries Inc.Inventors: Qing Liu, Xiuyu Cai, Ruilong Xie, Chun-chen Yeh, Kejia Wang, Daniel Chanemougame
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Publication number: 20170033197Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.Type: ApplicationFiled: June 14, 2016Publication date: February 2, 2017Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
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Publication number: 20170033221Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.Type: ApplicationFiled: July 29, 2015Publication date: February 2, 2017Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
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Publication number: 20160260741Abstract: In forming a finFET, a selective nitridation process is used during spacer formation on the gate to support a finer fin pitch than could be achieved using traditional spacer deposition processes. The spacer formation may also allow precise control over formation of source and drain junctions.Type: ApplicationFiled: May 16, 2016Publication date: September 8, 2016Applicants: STMicroelectronics, Inc., International Business Machines Corporation, GlobalFoundries IncInventors: Qing Liu, Chun-Chen Yeh, Ruilong Xie, Xiuyu Cai, Kejia Wang