Patents by Inventor Kejia Wang
Kejia Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8753912Abstract: Techniques for fabricating nanowire/microwire-based solar cells are provided. In one, a method for fabricating a solar cell is provided. The method includes the following steps. A doped substrate is provided. A monolayer of spheres is deposited onto the substrate. The spheres include nanospheres, microspheres or a combination thereof. The spheres are trimmed to introduce space between individual spheres in the monolayer. The trimmed spheres are used as a mask to pattern wires in the substrate. The wires include nanowires, microwires or a combination thereof. A doped emitter layer is formed on the patterned wires. A top contact electrode is deposited over the emitter layer. A bottom contact electrode is deposited on a side of the substrate opposite the wires.Type: GrantFiled: April 12, 2012Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: William Graham, Supratik Guha, Oki Gunawan, George S. Tulevski, Kejia Wang, Ying Zhang
-
Patent number: 8617915Abstract: In an annealing process, a Kesterite film is provided on a substrate. The Kesterite film and the substrate are generally planar, have an interface, and have a substrate exterior side and a Kesterite exterior side. An additional step includes locating the cap adjacent the Kesterite exterior side. A further step includes applying sufficient heat to the Kesterite film and the substrate for a sufficient time to anneal the Kesterite film. The annealing is carried out with the cap adjacent the Kesterite exterior side. In another aspect, the film is not limited to Kesterite, and the cap is employed without any precursor layer thereon. Solar cell manufacturing techniques employing the annealing techniques are also disclosed.Type: GrantFiled: June 3, 2011Date of Patent: December 31, 2013Assignee: International Business Machines CorporationInventors: Supratik Guha, David B. Mitzi, Teodor K. Todorov, Kejia Wang
-
Patent number: 8440497Abstract: A Kesterite film is vacuum deposited and annealed on a substrate. Deposition is conducted at low temperature to provide good composition control and efficient use of metals. Annealing is conducted at a high temperature for a short period of time. Thermal evaporation, E-beam evaporation or sputtering in a high vacuum environment may be employed as part of a deposition process.Type: GrantFiled: October 26, 2010Date of Patent: May 14, 2013Assignee: International Business Machines CorporationInventors: Supratik Guha, Kejia Wang
-
Publication number: 20130115732Abstract: Multi-crystalline silicon processing techniques are provided. In one aspect, a method for roughening a multi-crystalline silicon surface is provided. The method includes the following steps. The multi-crystalline silicon surface is coated with a diblock copolymer. The diblock copolymer is annealed to form nanopores therein. The multi-crystalline silicon surface is etched through the nanopores in the diblock copolymer to roughen the multi-crystalline silicon surface. The diblock copolymer is removed. A multi-crystalline silicon substrate with a roughened surface having a plurality of peaks and troughs is also provided, wherein a distance from one peak to an adjacent peak on the roughened surface is from about 20 nm to about 400 nm.Type: ApplicationFiled: November 4, 2011Publication date: May 9, 2013Applicant: International Business Machines CorporationInventors: Dechao Guo, Zhengwen Li, Kejia Wang, Zhen Zhang
-
Patent number: 8426241Abstract: Techniques for using electrodeposition to form absorber layers in diodes (e.g., solar cells) are provided. In one aspect, a method for fabricating a diode is provided. The method includes the following steps. A substrate is provided. A backside electrode is formed on the substrate. One or more layers are electrodeposited on the backside electrode, wherein at least one of the layers comprises copper, at least one of the layers comprises zinc and at least one of the layers comprises tin. The layers are annealed in an environment containing a sulfur source to form a p-type CZTS absorber layer on the backside electrode. An n-type semiconductor layer is formed on the CZTS absorber layer. A transparent conductive layer is formed on the n-type semiconductor layer. A diode is also provided.Type: GrantFiled: September 9, 2010Date of Patent: April 23, 2013Assignee: International Business Machines CorporationInventors: Shafaat Ahmed, Hariklia Deligianni, Lubomyr T. Romankiw, Kejia Wang
-
Publication number: 20120326125Abstract: A semiconductor device includes a substrate, a nanowire, a first structure, and a second structure. The nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate, where the nanowire includes a layer on a surface of the nanowire, where the layer includes at least one of silicide and carbide, where the layer has a substantially uniform shape.Type: ApplicationFiled: September 6, 2012Publication date: December 27, 2012Applicant: International Business Machines CorporationInventors: Dechao Guo, Zhengwen Li, Kejia Wang, Zhen Zhang, Yu Zhu
-
Publication number: 20120196401Abstract: Techniques for fabricating nanowire/microwire-based solar cells are provided. In one, a method for fabricating a solar cell is provided. The method includes the following steps. A doped substrate is provided. A monolayer of spheres is deposited onto the substrate. The spheres include nanospheres, microspheres or a combination thereof. The spheres are trimmed to introduce space between individual spheres in the monolayer. The trimmed spheres are used as a mask to pattern wires in the substrate. The wires include nanowires, microwires or a combination thereof. A doped emitter layer is formed on the patterned wires. A top contact electrode is deposited over the emitter layer. A bottom contact electrode is deposited on a side of the substrate opposite the wires.Type: ApplicationFiled: April 12, 2012Publication date: August 2, 2012Applicant: International Business Machines CorporationInventors: William Graham, Supratik Guha, Oki Gunawan, George S. Tulevski, Kejia Wang, Ying Zhang
-
Publication number: 20120187375Abstract: In one exemplary embodiment, a method includes: providing a semiconductor device having a substrate, a nanowire, a first structure and a second structure, where the nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate; and performing atomic layer deposition to deposit a film on at least a portion of the semiconductor device, where performing atomic layer deposition to deposit the film includes performing atomic layer deposition to deposit the film on at least a surface of the nanowire.Type: ApplicationFiled: January 25, 2011Publication date: July 26, 2012Applicant: International Business Machines CorporationInventors: Dechao Guo, Zhengwen Li, Kejia Wang, Zhen Zhang, Yu Zhu
-
Patent number: 8211735Abstract: Techniques for fabricating nanowire/microwire-based solar cells are provided. In one, a method for fabricating a solar cell is provided. The method includes the following steps. A doped substrate is provided. A monolayer of spheres is deposited onto the substrate. The spheres include nanospheres, microspheres or a combination thereof The spheres are trimmed to introduce space between individual spheres in the monolayer. The trimmed spheres are used as a mask to pattern wires in the substrate. The wires include nanowires, microwires or a combination thereof A doped emitter layer is formed on the patterned wires. A top contact electrode is deposited over the emitter layer. A bottom contact electrode is deposited on a side of the substrate opposite the wires.Type: GrantFiled: June 8, 2009Date of Patent: July 3, 2012Assignee: International Business Machines CorporationInventors: William Graham, Supratik Guha, Oki Gunawan, George S. Tulevski, Kejia Wang, Ying Zhang
-
Publication number: 20120100664Abstract: A Kesterite film is vacuum deposited and annealed on a substrate. Deposition is conducted at low temperature to provide good composition control and efficient use of metals. Annealing is conducted at a high temperature for a short period of time. Thermal evaporation, E-beam evaporation or sputtering in a high vacuum environment may be employed as part of a deposition process.Type: ApplicationFiled: October 26, 2010Publication date: April 26, 2012Applicant: International Business Machines CorporationInventors: Supratik Guha, Kejia Wang
-
Publication number: 20120100663Abstract: Techniques for fabricating thin film solar cells are provided. In one aspect, a method of fabricating a solar cell includes the following steps. A molybdenum (Mo)-coated substrate is provided. Absorber layer constituent components, two of which are sulfur (S) and selenium (Se), are deposited on the Mo-coated substrate. The S and Se are deposited on the Mo-coated substrate using thermal evaporation in a vapor chamber. Controlled amounts of the S and Se are introduced into the vapor chamber to regulate a ratio of the S and Se provided for deposition. The constituent components are annealed to form an absorber layer on the Mo-coated substrate. A buffer layer is formed on the absorber layer. A transparent conductive electrode is formed on the buffer layer.Type: ApplicationFiled: October 26, 2010Publication date: April 26, 2012Applicant: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Supratik Guha, Byungha Shin, Kejia Wang
-
Publication number: 20120097234Abstract: Techniques for fabricating thin film solar cells, such as CuZnSn(S,Se) (CZTSSe) solar cells are provided. In one aspect, a method of fabricating a solar cell is provided that includes the following steps. A substrate is provided. The substrate is coated with a molybdenum (Mo) layer. A stress-relief layer is deposited on the Mo layer. The stress-relief layer is coated with a diffusion barrier. Absorber layer constituent components are deposited on the diffusion barrier, wherein the constituent components comprise one or more of sulfur (S) and selenium (Se). The constituent components are annealed to form an absorber layer, wherein the stress-relief layer relieves thermal stress imposed on the absorber layer, and wherein the diffusion barrier blocks diffusion of the one or more of S and Se into the Mo layer. A buffer layer is formed on the absorber layer. A transparent conductive electrode is formed on the buffer layer.Type: ApplicationFiled: October 26, 2010Publication date: April 26, 2012Applicant: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Supratik Guha, Byungha Shin, Kejia Wang
-
Publication number: 20120070936Abstract: In an annealing process, a Kesterite film is provided on a substrate. The Kesterite film and the substrate are generally planar, have an interface, and have a substrate exterior side and a Kesterite exterior side. An additional step includes locating the cap adjacent the Kesterite exterior side. A further step includes applying sufficient heat to the Kesterite film and the substrate for a sufficient time to anneal the Kesterite film. The annealing is carried out with the cap adjacent the Kesterite exterior side. In another aspect, the film is not limited to Kesterite, and the cap is employed without any precursor layer thereon. Solar cell manufacturing techniques employing the annealing techniques are also disclosed.Type: ApplicationFiled: June 3, 2011Publication date: March 22, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Supratik Guha, David B. Mitzi, Teodor K. Todorov, Kejia Wang
-
Publication number: 20120061790Abstract: Techniques for using electrodeposition to form absorber layers in diodes (e.g., solar cells) are provided. In one aspect, a method for fabricating a diode is provided. The method includes the following steps. A substrate is provided. A backside electrode is formed on the substrate. One or more layers are electrodeposited on the backside electrode, wherein at least one of the layers comprises copper, at least one of the layers comprises zinc and at least one of the layers comprises tin. The layers are annealed in an environment containing a sulfur source to form a p-type CZTS absorber layer on the backside electrode. An n-type semiconductor layer is formed on the CZTS absorber layer. A transparent conductive layer is formed on the n-type semiconductor layer. A diode is also provided.Type: ApplicationFiled: September 9, 2010Publication date: March 15, 2012Applicant: International Business Machines CorporationInventors: Shafaat Ahmed, Hariklia Deligianni, Lubomyr T. Romankiw, Kejia Wang
-
Publication number: 20100221866Abstract: Techniques for fabricating nanowire/microwire-based solar cells are provided. In one, a method for fabricating a solar cell is provided. The method includes the following steps. A doped substrate is provided. A monolayer of spheres is deposited onto the substrate. The spheres include nanospheres, microspheres or a combination thereof The spheres are trimmed to introduce space between individual spheres in the monolayer. The trimmed spheres are used as a mask to pattern wires in the substrate. The wires include nanowires, microwires or a combination thereof A doped emitter layer is formed on the patterned wires. A top contact electrode is deposited over the emitter layer. A bottom contact electrode is deposited on a side of the substrate opposite the wires.Type: ApplicationFiled: June 8, 2009Publication date: September 2, 2010Applicant: International Business Machines CorporationInventors: William Graham, Supratik Guha, Oki Gunawan, George S. Tulevski, Kejia Wang, Ying Zhang