Abstract: A magnetic erasable writable material for large format applications is disclosed, and includes a cast polyvinylchloride film with a mount surface opposite an etched receiver surface. Also incorporated is a transparent polyester film that has a marking side with a first predetermined hardness and an opposite seal side, laminated to the receiver surface. The marking side includes a clear superstrate that has a second predetermined hardness and applied to the marking side of the polyester film to lower its surface energy. The receiver surface is treated to have a surface energy adjusted to enable improved adherence of printed and preformed graphic elements, which are encapsulated when laminated between the PET film and receiver surface. The superstrate includes a perfluoropolyether, a polyurethane, an acrylated polyurethane, and/or an acrylate resin to harden the material.

Abstract: Systems and methods for MEMS devices are disclosed. A microelectromechanical system (MEMS) device includes a substrate, and a MEMS structure supported by the substrate. The MEMS structure includes a first layer of a first material comprising a titanium aluminum alloy. The MEMS structure furth includes an aluminum layer on the first layer.

Abstract: A magnetic erasable writable material for large format applications is disclosed, and includes a cast polyvinylchloride film with a mount surface opposite an etched receiver surface. Also incorporated is a transparent polyester film that has a marking side with a first predetermined hardness and an opposite seal side, laminated to the receiver surface. The marking side includes a clear superstrate that has a second predetermined hardness and applied to the marking side of the polyester film to lower its surface energy. The receiver surface is treated to have a surface energy adjusted to enable improved adherence of printed and preformed graphic elements, which are encapsulated when laminated between the PET film and receiver surface. The superstrate includes a perfluoropolyether, a polyurethane, an acrylated polyurethane, and/or an acrylate resin to harden the material.

Abstract: An erasable writable material for large format applications is disclosed, and includes a cast polyvinylchloride film with a mount surface opposite an etched receiver surface. Also incorporated is a transparent polyester film that has a marking side with a hardness exceeding approximately shore D 79 and an opposite seal side, hermetically laminated to the receiver surface. The marking side includes a clear superstrate that has a hardness exceeding approximately shore D 90, which is applied to the marking side of the polyester film to lower surface energy below about 24 millinewtons per meter. The receiver surface is treated to have a surface energy exceeding about 45 millinewtons per meter, to enable improved adherence of printed and preformed graphic elements, which are encapsulated when laminated between the PET film and receiver surface. The superstrate includes a perfluoropolyether, a polyurethane, an acrylated polyurethane, and/or an acrylate resin to harden the material.

Abstract: A magnetic erasable writable material for large format applications is disclosed, and includes a cast polyvinylchloride film with a mount surface opposite an etched receiver surface. Also incorporated is a transparent polyester film that has a marking side with a hardness exceeding approximately shore D 79 and an opposite seal side, hermetically laminated to the receiver surface. The marking side includes a clear superstrate that has a hardness exceeding approximately shore D 90, which is applied to the marking side of the polyester film to lower surface energy below about 24 millinewtons per meter. The receiver surface is treated to have a surface energy exceeding about 45 millinewtons per meter, to enable improved adherence of printed and preformed graphic elements, which are encapsulated when laminated between the PET film and receiver surface. The superstrate includes a perfluoropolyether, a polyurethane, an acrylated polyurethane, and/or an acrylate resin to harden the material.

Abstract: This disclosure relates to a method of presenting user interactive graphical content. More specifically, the disclosure relates to presentation of a writeable surface covering including a base layer displaying graphical content and a transparent layer applied to the base layer. Users may add user content to the writeable surface covering, such as, by writing or drawing on the covering using dry erase markers other suitable writing implements. The user content may overlay the graphical content without marring the graphical content, and the user content may later be erased from the writeable surface covering. The writeable surface covering may be adhered or otherwise attached to a wall or other support surface.

Abstract: An erasable writable material for large format applications is disclosed, and includes a cast polyvinylchloride film with a mount surface opposite an etched receiver surface. Also incorporated is a transparent polyester film that has a marking side with a hardness exceeding approximately shore D 79 and an opposite seal side, hermetically laminated to the receiver surface. The marking side includes a clear superstrate that has a hardness exceeding approximately shore D 90, which is applied to the marking side of the polyester film to lower surface energy below about 24 millinewtons per meter. The receiver surface is treated to have a surface energy exceeding about 45 millinewtons per meter, to enable improved adherence of printed and preformed graphic elements, which are encapsulated when laminated between the PET film and receiver surface. The superstrate includes a perfluoropolyether, a polyurethane, an acrylated polyurethane, and/or an acrylate resin to harden the material.

Abstract: In described examples, a MEMS device is formed by forming a sacrificial layer over a substrate and forming a first metal layer over the sacrificial layer. Subsequently, the first metal layer is exposed to an oxidizing ambient which oxidizes a surface layer of the first metal layer where exposed to the oxidizing ambient, to form a native oxide layer of the first metal layer. A second metal layer is subsequently formed over the native oxide layer of the first metal layer. The sacrificial layer is subsequently removed, forming a released metal structure.

Abstract: In described examples, a MEMS device is formed by forming a sacrificial layer over a substrate and forming a first metal layer over the sacrificial layer. Subsequently, the first metal layer is exposed to an oxidizing ambient which oxidizes a surface layer of the first metal layer where exposed to the oxidizing ambient, to form a native oxide layer of the first metal layer. A second metal layer is subsequently formed over the native oxide layer of the first metal layer. The sacrificial layer is subsequently removed, forming a released metal structure.

Abstract: A MEMS device is formed by forming a sacrificial layer over a substrate and forming a first metal layer over the sacrificial layer. Subsequently, the first metal layer is exposed to an oxidizing ambient which oxidizes a surface layer of the first metal layer where exposed to the oxidizing ambient, to form a native oxide layer of the first metal layer. A second metal layer is subsequently formed over the native oxide layer of the first metal layer. The sacrificial layer is subsequently removed, forming a released metal structure.

Abstract: A MEMS device is formed by forming a sacrificial layer over a substrate and forming a first metal layer over the sacrificial layer. Subsequently, the first metal layer is exposed to an oxidizing ambient which oxidizes a surface layer of the first metal layer where exposed to the oxidizing ambient, to form a native oxide layer of the first metal layer. A second metal layer is subsequently formed over the native oxide layer of the first metal layer. The sacrificial layer is subsequently removed, forming a released metal structure.

Abstract: Disclosed is a method of fabricating an integrated circuit comprising patterning a dielectric layer to form a hole having a sidewall and a bottom. The hole can expose an underlying material of an electrically conducting material. The method also includes exposing the sidewall and the exposed underlying material to a plasma etch, depositing a barrier layer on the bottom and the sidewall of the hole after the plasma etch clean, forming a counter-sunk cone in the underlying material by etching through the barrier layer at the bottom of the hole into the conducting metal underneath, flash depositing a thin layer of the barrier material into the hole, and finally depositing a metal seed layer in the hole covering the sidewalls and the bottom of the hole including the cone at the bottom. The hole is finally filled by depositing a metal layer in the hole.

Abstract: Reducing chemical contaminants is increasingly important for maintaining competitive production costs during fabrication of electronic devices. There is currently no production floor capability for mapping chemical contaminants across an electronic device substrate on a routine basis. A scanning surface chemical analyzer for mapping the distributions of a variety of chemicals on substrates is disclosed. The analyzer includes an array of sensors, each of which detects a single chemical or narrow range of chemicals, a scanning mechanism to provide a mapping capability, an electrical signal analyzer to collect and analyze signals from the array of sensors and generate reports of chemical distributions, and an optical desorption mechanism to amplify detection. A preferred embodiment includes an array of miniature quadrupole mass spectrometers in the sensor array. Scanning modes include whole substrate mapping, region sampling, and spot sampling of known defect sites.

Abstract: Reducing chemical contaminants is increasingly important for maintaining competitive production costs during fabrication of electronic devices. There is currently no production floor capability for mapping chemical contaminants across an electronic device substrate on a routine basis. A scanning surface chemical analyzer for mapping the distributions of a variety of chemicals on substrates is disclosed. The analyzer includes an array of sensors, each of which detects a single chemical or narrow range of chemicals, a scanning mechanism to provide a mapping capability, an electrical signal analyzer to collect and analyze signals from the array of sensors and generate reports of chemical distributions, and an optical desorption mechanism to amplify detection. A preferred embodiment includes an array of miniature quadrupole mass spectrometers in the sensor array. Scanning modes include whole substrate mapping, region sampling, and spot sampling of known defect sites.

Abstract: Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.

Abstract: A system comprising a first layer comprising one or more metal sub-layers and a protective overcoat (PO) layer adjacent to the first layer. The PO layer is adapted to protect the first layer, and a circuit logic is at least partially embedded within the PO layer. The circuit logic couples to one of the metal sub-layers.

Abstract: An embodiment of the invention is a method of fabricating a haze free, phase pure, PZT layer, 3, where a lead rich PZT film, 102, is formed over a phase pure stoichiometric PZT film, 101.

Abstract: The present invention provides a method of forming a interconnect barrier layer 100. In the method, physical vapor deposition of barrier material 200 is performed within an opening 140 located in a dielectric layer 135 of a substrate 110. RF plasma etching of the barrier material 200 that is deposited in the opening 140 occurs simultaneously with conducting the physical vapor deposition of the barrier material 200.

Abstract: The present invention provides a ferroelectric capacitor, a method of manufacture therefor, and a method of manufacturing a ferroelectric random access memory (FeRAM) device. The ferroelectric capacitor (100), among other elements, includes a substantially planar ferroelectric dielectric layer (165) located over a first electrode layer (160), wherein the substantially planar ferroelectric dielectric layer (165) has an average surface roughness of less than about 4 nm. The ferroelectric capacitor (100) further includes a second electrode layer (170) located over the substantially planar ferroelectric dielectric layer (165).

Abstract: The present invention provides, in one embodiment, method of forming a barrier layer 300 over a semiconductor substrate 110. The method comprises forming an opening 120 in an insulating layer 130 located over a substrate thereby uncovering an underlying copper layer 140. The method further comprises exposing the opening and the underlying copper layer to a plasma-free reducing atmosphere 200 in the presence of a thermal anneal. The also comprises depositing a barrier layer in the exposed opening and on the exposed underlying copper layer. Such methods and resulting conductive structures thereof may be advantageously used in methods to manufacture integrated circuits comprising copper interconnects.