Patents by Inventor Kelly Malone
Kelly Malone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7396758Abstract: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05?v?0.8, 0?w?0.9, 0.05?x?0.8, 0?y?0.3, 0.05?z?0.08 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.Type: GrantFiled: January 3, 2007Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: Elbert E. Huang, Kaushik A. Kumar, Kelly Malone, Dirk Pfeiffer, Muthumanickam Sankarapandian, Christy S. Tyberg
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Publication number: 20080157270Abstract: The embodiments of the invention generally relate to fuse and anti-fuse structures and include a copper conductor positioned within a substrate and a metal cap on the first conductor. A low-k dielectric is on the substrate and the metal cap. A tantalum nitride resistor is on the dielectric, and the resistor is positioned above the metal cap such that an antifuse element region of the dielectric is positioned between the resistor and the metal cap. The antifuse element region of the dielectric is adapted to change resistance values by application of a voltage difference between the resistor and the copper conductor/metal cap. The antifuse element region has a first higher resistance (more closely matching an insulator) before application of the voltage and a second lower resistance (more closely matching a conductor) after application of such voltage.Type: ApplicationFiled: December 30, 2006Publication date: July 3, 2008Inventors: Deok-kee Kim, Anil K. Chinthakindi, Son Van Nguyen, Kelly Malone, Byeongju Park
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Publication number: 20080157268Abstract: A programmable structure such as a write once read many (WORM) or one time programmable read only memories (OTPROM) is disclosed herein. The structure includes a first conductor (such as copper) positioned within a substrate and a metal cap on the first conductor. A low-k dielectric is on the substrate and the metal cap. A tantalum nitride resistor is on the dielectric, and the resistor is positioned above the metal cap such that a programmable region of the dielectric is positioned between the resistor and the metal cap. The first conductor (including the metal cap), the programmable region of the dielectric, and the resistor form a metal-insulator-metal capacitor. Further, the programmable region of the dielectric is adapted to be permanently changed from heat produced by the resistor when a voltage difference is applied to the first and second ends of the resistor, respectively, through the first and second contacts.Type: ApplicationFiled: December 30, 2006Publication date: July 3, 2008Inventors: Deok-kee Kim, Anil K. Chinthakindi, Kelly Malone, Son Van Nguyen, Byeongju Park
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Publication number: 20080147262Abstract: A system and method for providing customized help to a vehicle user when a vehicle problem is detected. The method includes detecting vehicle data that indicates a condition of a vehicle and obtaining profile data comprising an estimated mechanical skill level of a user. The method further includes providing instructions, based upon the profile data and the vehicle data, to the user for addressing the condition.Type: ApplicationFiled: December 15, 2006Publication date: June 19, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORP.Inventors: Fonda DANIELS, Deirdre H. DUTHIL, Sandra K. JOHNSON, Ruthie D. LYLE, Kelly MALONE, Demethria Johnson RAMSEUR
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Publication number: 20080124815Abstract: The present invention provides a method for repairing a damaged insulating layer in a semiconductor device comprising pre-cleaning the damaged insulating layer of the semiconductor device, depositing a CNH polymeric cap material on said damaged insulating layer, wherein said polymeric cap material comprises between about 10 and about 90 atomic percent C, between about 10 and about 70 atomic percent N, between about 10 and about 55 atomic percent H and at least one active vinyl group following deposition, depositing a further polymeric cap material on said deposited CNH polymeric cap material and treating said semiconductor device with UV irradiation to effectively repair the damaged insulating layer.Type: ApplicationFiled: November 3, 2006Publication date: May 29, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kelly Malone, Son Van Nguyen
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Publication number: 20080109723Abstract: Provided are techniques for providing context-based user assistance. A request from a user for user assistance content for a first configurable element is received. One or more rules are retrieved for the first configurable element, wherein at least one of the rules describes a second configurable element that is related to the first configurable element. The one or more rules are used to identify context-based user assistance content for configuring at least one of the first configurable element and the second configurable element. The user assistance content is provided to the user.Type: ApplicationFiled: November 7, 2006Publication date: May 8, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mary Catherine Burton, Fonda J. Daniels, Sandra K. Johnson, Ruthie D. Lyle, Kelly Malone, LaTondra Alyce Murray, Demethria Johnson Ramseur
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Publication number: 20080099923Abstract: A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous line level low-k dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous line level low-k dielectric; a second thin non-porous via level low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.Type: ApplicationFiled: January 3, 2008Publication date: May 1, 2008Inventors: Kaushik Kumar, Kelly Malone, Christy Tyberg
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Patent number: 7338895Abstract: A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous low-k line level dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous low-k dielectric; a second thin non-porous low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.Type: GrantFiled: January 26, 2006Date of Patent: March 4, 2008Assignee: International Business Machines CorporationInventors: Kaushik A Kumar, Kelly Malone, Christy S Tyberg
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Publication number: 20070284736Abstract: The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer.Type: ApplicationFiled: May 18, 2006Publication date: December 13, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chih-Chao Yang, Griselda Bonilla, Shyng-Tsong Chen, Kelly Malone
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Publication number: 20070222081Abstract: When an interconnect structure is built on porous ultra low k (ULK) material, the bottom of the trench and/or via is usually damaged by a following metallization process which may be suitable for dense higher dielectric materials. Embodiment of the present invention may provide a method of forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes steps of treating an exposed area of said ILD material to create a densified area, and metallizing said densified area.Type: ApplicationFiled: March 23, 2006Publication date: September 27, 2007Applicant: International business machine corporationInventors: Shyng-Tsong Chen, Qinghung Lin, Kelly Malone, Sanjay Mehta, Terry Spooner, Chih-Chao Yang
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Publication number: 20070111509Abstract: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05?v?0.8, 0?w?0.9, 0.05?x?0.8, 0?y?0.3, 0.05?z?0.08 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.Type: ApplicationFiled: January 3, 2007Publication date: May 17, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Elbert Huang, Kaushik Kumar, Kelly Malone, Dirk Pfeiffer, Muthumanickam Sankarapandian, Christy Tyberg
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Patent number: 7187081Abstract: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05?v?0.8, 0?w?0.9, 0.05?x?0.8, 0?y?0.3, 0.05?z?0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.Type: GrantFiled: October 31, 2003Date of Patent: March 6, 2007Assignee: International Business Machines CorporationInventors: Elbert E. Huang, Kaushik A. Kumar, Kelly Malone, Dirk Pfeiffer, Muthumanickam Sankarapandian, Christy S. Tyberg
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Publication number: 20070048981Abstract: A method for protecting a semiconductor device from carbon depletion type damage includes enriching an exposed surface of a porous interlevel dielectric material (ILD) with a carbon based material, and implementing a plasma based operation on the porous ILD material. The enriching of the porous ILD material reduces effects of carbon depletion as a result of the plasma based operation.Type: ApplicationFiled: September 1, 2005Publication date: March 1, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Griselda Bonilla, Richard Conti, Timothy Dalton, Nicholas Fuller, Kelly Malone, Satyanarayana Nitta, Shom Ponoth
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Publication number: 20060277263Abstract: A method for preparing and replying to multi-party e-mails is provided. The method includes opening an e-mail composition window in an e-mail application for generating an e-mail, specifying one or more recipients from a plurality of recipient groups for the e-mail, creating one or more response sections, identifying at least one recipient for each of the response sections, and sending the e-mail. The creating step further includes creating a general section in the e-mail. The method further includes selecting a delivery option from a plurality of delivery options for the e-mail prior to sending the e-mail and receiving one or more return receipts based on the delivery option selected in the e-mail sent. The method further includes selecting a response section in a received e-mail, and generating a reply to the response section in a reply e-mail composition window containing the response section.Type: ApplicationFiled: June 7, 2005Publication date: December 7, 2006Applicant: International Business Machines CorporationInventors: Fonda Daniels, Ruthie Lyle, Kelly Malone, Demethria Ramseur
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Publication number: 20060264036Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.Type: ApplicationFiled: July 24, 2006Publication date: November 23, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shyng-Tsong Chen, Stefanie Chiras, Matthew Colburn, Tomothy Dalton, Jeffrey Hedrick, Elbert Huang, Kaushik Kumar, Michael Lane, Kelly Malone, Chandrasekhar Narayan, Satyanarayana Nitta, Sampath Purushothaman, Robert Rosenberg, Christy Tyberg, Roy Yu
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Patent number: 7084479Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.Type: GrantFiled: December 8, 2003Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Shyng-Tsong Chen, Stefanie Ruth Chiras, Matthew Earl Colburn, Timothy Joseph Dalton, Jeffrey Curtis Hedrick, Elbert Emin Huang, Kaushik Arun Kumar, Michael Wayne Lane, Kelly Malone, Chandrasekhar Narayan, Satyanarayana Venkata Nitta, Sampath Purushothaman, Robert Rosenburg, Christy Sensenich Tyberg, Roy RongQing Yu
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Publication number: 20060128163Abstract: Damaged porous OSG layers and other damage may be chemically healed. Chemical healing is particularly advantageous in a porous OSG layer in a sub 90 nm ILD. For example, chemical healing may be by reacting the damage with an adhesion promoter having a âkâ value comparable to the âkâ value desired in the damaged material. Damaged porous OSG layers (which are hydrophilic) may be manipulated to prevent them from allowing moisture to reach copper lines. Undesirable copper out-diffusion can be controlled in ILDs having porous OSG geometry.Type: ApplicationFiled: December 14, 2004Publication date: June 15, 2006Applicant: International Business Machines CorporationInventors: Shyng-Tsong Chen, Kaushik Kumar, Kelly Malone
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Publication number: 20060118961Abstract: A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous low-k line level dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous low-k dielectric; a second thin non-porous low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.Type: ApplicationFiled: January 26, 2006Publication date: June 8, 2006Inventors: Kaushik Kumar, Kelly Malone, Christy Tyberg
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Patent number: 7057287Abstract: A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous low-k line level dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous low-k dielectric; a second thin non-porous low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.Type: GrantFiled: August 21, 2003Date of Patent: June 6, 2006Assignee: International Business Machines CorporationInventors: Kaushik A Kumar, Kelly Malone, Christy S Tyberg
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Publication number: 20050127514Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.Type: ApplicationFiled: December 8, 2003Publication date: June 16, 2005Inventors: Shyng-Tsong Chen, Stefanie Chiras, Matthew Colburn, Timothy Dalton, Jeffrey Hedrick, Elbert Huang, Kaushik Kumar, Michael Lane, Kelly Malone, Chandrasekhar Narayan, Satyanarayana Nitta, Sampath Purushothaman, Robert Rosenberg, Christy Tyberg, Roy Yu