Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

Abstract: Density-graded adhesion layers on conductive structures within a microelectronic package substrate are described. An example is a density-graded adhesion layer that includes a dense region proximate to a conductive structure that is surrounded by a less dense (or porous) region adjacent to an overlying dielectric layer. Providing such a graded adhesion layer can have a number of benefits, which can include providing both mechanical connections for improved adhesion with a surrounding dielectric layer and provide hermetic protection for the underlying conductive structure from corrosive species. The adhesion layer enables the conductive structure to maintain its as-formed smooth surface which in turn reduces insertion loss of signals transmitted through the conductive structure.

Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.

Abstract: Embodiments include package substrates and methods of forming the package substrates. A package substrate includes a first conductive layer in a first dielectric, a second dielectric over the first dielectric, and a second conductive layer in the second dielectric, where the second conductive layer includes first and second traces. The package substrate also includes a third conductive layer over the second dielectric, and a high dielectric constant (Dk) and low DK regions in the first and second dielectrics, where the high Dk region surrounds the first traces, and where the low Dk region surrounds the second traces. The high Dk region may be between the first and third conductive layers. The low Dk region may be between the first and third conductive layers. The package substrate may include a dielectric region in the first and second dielectrics, where the dielectric region separates the high Dk and low Dk regions.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first trace embedded in a package substrate. In an embodiment, the first trace comprises a first region, where the first region has a first width, and a second region, where the second region has a second width that is smaller than the first width.

Abstract: Electrical connector technology is disclosed. In one example, a connector for coupling an electronics sub-assembly to an electronics assembly comprises a connector body having and a sub-assembly interface configured to electrically couple to an electronics sub-assembly. The connector has a circuit board interface configured to electrically couple to a circuit board of an electronics assembly. The connector has at least two rows of contacts configured to electrically couple the circuit board to the electronics sub-assembly. The at least two rows of contacts are aligned offset relative to each other such that any ground contact of one row avoids intersection of a plane in which any ground contact of the other row resides to at least partially cancel row-to-row crosstalk when the at least two rows of contacts are transmitting signals at a predetermined high-speed bit rate.

Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.

Abstract: An interposer and method of providing spatial and arrangement transformation are described. An electronic system has an electronic package, a motherboard and an interposer between the package and the motherboard. The interposer has signal and ground contacts on opposing surfaces that are respectively connected. The contacts opposing the package has a higher signal to ground contact ratio than the contacts opposing the motherboard, as well as different arrangements. Ground shielding vias in the interposer, which are connected to a ground plane, electrically isolate the signals through the interposer. The package may be mounted on a shielded socket such that signal and ground pins are mounted respectively in signal and ground socket mountings, ground shielding vias are between the signal socket mountings, and the ground socket mountings contain plated socket housings.

Abstract: An electronic device package is described. The electronic device package includes one or more dies. The electronic device package includes an interposer coupled to the one or more dies. The electronic device package also includes a package substrate coupled to the interposer. The electronic device package includes a plurality of through-silicon vias (TSVs) in at least one die of the one or more dies, or the interposer, or both. The electronic device package includes a passive equalizer structure communicatively coupled to a TSV pair in the plurality of TSVs. The passive equalizer structure is operable to minimize a level of insertion loss variation in the TSV pair.

Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

Abstract: Semiconductor packages with through bridge die connections and a method of manufacture therefor is disclosed. The semiconductor packages may house one or more electronic components as a system in a package (SiP) implementation. A bridge die, such as an embedded multi-die interconnect bridge (EMIB), may be embedded within one or more build-up layers of the semiconductor package. The bridge die may have an electrically conductive bulk that may be electrically connected on a backside to a power plane and used to deliver power to one or more dies attached to the semiconductor package via interconnects formed on a topside of the bridge die that are electrically connected to the bulk of the bridge die. A more direct path for power delivery through the bridge die may be achieved compared to routing power around the bridge die.

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

Abstract: An interposer and method of providing spatial and arrangement transformation are described. An electronic system has an electronic package, a motherboard and an interposer between the package and the motherboard. The interposer has signal and ground contacts on opposing surfaces that are respectively connected. The contacts opposing the package has a higher signal to ground contact ratio than the contacts opposing the motherboard, as well as different arrangements. Ground shielding vias in the interposer, which are connected to a ground plane, electrically isolate the signals through the interposer. The package may be mounted on a shielded socket such that signal and ground pins are mounted respectively in signal and ground socket mountings, ground shielding vias are between the signal socket mountings, and the ground socket mountings contain plated socket housings.

Abstract: Passive semiconductor components and switches may be formed directly in, on, about, or across each of two or more semiconductor dies included in a stacked-die semiconductor package. At least some of the passive semiconductor components and/or switches may be formed in redistribution layers operably coupled to corresponding semiconductor dies included in the stacked-die semiconductor package. The switches may have multiple operating states and may be operably coupled to the passive semiconductor components such that one or more passive semiconductor components may be selectively included in one or more circuits or excluded from one or more circuits. The switches may be manually controlled or autonomously controlled using one or more control circuits. The one or more control circuits may receive one or more input signals containing host system information and/or data that is used to adjust or set the operating state of at least some of the switches.

Abstract: An interposer layer includes an integral waveguide to facilitate high speed (e.g., greater than 80 GHz) communication between semiconductor dies in a semiconductor package. An interposer layer may include a waveguide member and a dielectric layer disposed adjacent at least a portion of an exterior perimeter of the waveguide member. The waveguide member includes a material having a first relative permittivity. The dielectric member includes a material having a second relative permittivity that is less than the first relative permittivity. The waveguide member and the dielectric member form an interposer layer having an upper surface and a lower surface. A first conductive sheet may be disposed proximate the upper surface of the interposer layer and a second conductive sheet may be disposed proximate the lower surface of the interposer layer.

Abstract: Discussed generally herein are methods and devices for multichip packages that include an inorganic interposer. A device can include a substrate including low density interconnect circuitry therein, an inorganic interposer on the substrate, the inorganic interposer including high density interconnect circuitry electrically connected to the low density interconnect circuitry, the inorganic interposer including inorganic materials, and two or more chips electrically connected to the inorganic interposer, the two or more chips electrically connected to each other through the high density interconnect circuitry.

Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.

Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.

Abstract: Embodiments include electronic packages and methods of forming such packages. An electronic package includes a memory module comprising a first memory die. The first memory die includes first interconnects with a first pad pitch and second interconnects with a second pad pitch, where the second pad pitch is less than the first pad pitch. The memory module also includes a redistribution layer below the first memory die, and a second memory die below the redistribution layer, where the second memory die has first interconnects with a first pad pitch and second interconnects with a second pad pitch. The memory module further includes a mold encapsulating the second memory die, where through mold interconnects (TMIs) provide an electrical connection from the redistribution layer to mold layer. The TMIs may be through mold vias. The TMIs may be made through a passive interposer that is encapsulated in the mold.