Patents by Inventor Kenichi Onisawa

Kenichi Onisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8344382
    Abstract: Provided is a method of promoting a deposition of semiconductor crystal nuclei on an insulating film such as a silicon oxide film even at a low temperature of 450° C. or lower in a reactive thermal CVD method. As one means thereof, a first semiconductor film is formed on an insulating substrate, and then semiconductor crystal nuclei are formed on parts of the first semiconductor film and simultaneously the first semiconductor film other than that in forming regions of the semiconductor crystal nuclei and their peripheries is removed by etching. Thereafter, a second semiconductor film is formed with using the semiconductor crystal nuclei as seeds.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: January 1, 2013
    Assignees: Hitachi, Ltd., Tokyo Institute of Technology
    Inventors: Junichi Hanna, Isao Suzumura, Mieko Matsumura, Mutsuko Hatano, Kenichi Onisawa, Masatoshi Wakagi, Etsuko Nishimura, Akiko Kagatsume
  • Patent number: 8093585
    Abstract: Each TFT for driving each of a plurality of pixels arranged in a matrix-like configuration is configured using a stagger-type polycrystalline-Si TFT. A gate electrode, which is composed of a high-heat-resistant material capable of resisting high temperature at the time of polycrystalline-Si film formation, is disposed at a lower layer as compared with the polycrystalline-Si layer that forms a channel of each TFT. A gate line, which is composed of a low-resistance material, is disposed at an upper layer as compared with the polycrystalline-Si layer. The gate electrode and the gate line are connected to each other via a through-hole bored in a gate insulation film. Respective configuration components of each organic electro-luminescent element are partially co-used at the time of the line formation, thereby suppressing an increase in the steps, processes, and configuration components.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: January 10, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Etsuko Nishimura, Masatoshi Wakagi, Kenichi Onisawa, Mieko Matsumura
  • Publication number: 20110108841
    Abstract: Provided is a method of promoting a deposition of semiconductor crystal nuclei on an insulating film such as a silicon oxide film even at a low temperature of 450° C. or lower in a reactive thermal CVD method. As one means thereof, a first semiconductor film is formed on an insulating substrate, and then semiconductor crystal nuclei are formed on parts of the first semiconductor film and simultaneously the first semiconductor film other than that in forming regions of the semiconductor crystal nuclei and their peripheries is removed by etching. Thereafter, a second semiconductor film is formed with using the semiconductor crystal nuclei as seeds.
    Type: Application
    Filed: June 26, 2009
    Publication date: May 12, 2011
    Inventors: Junichi Hanna, Isao Suzumura, Mieko Matsumura, Mutsuko Hatano, Kenichi Onisawa, Masatoshi Wakagi, Etsuko Nishimura, Akiko Kagatsume
  • Patent number: 7629743
    Abstract: The present invention provides OLEDs of the top emission type comprising organic light-emitting (LE) elements by preventing the problems such as the widening of the power lines, the reduction in the aperture ratio caused by the widening of the upper and the lower capacitor electrodes and the short circuit between the upper and the lower electrodes caused by the roughness of the flattening layers. Two kinds of the OLEDs are provided. One is an OLED comprising a region of LE layer sandwiched between the upper and lower electrodes is formed on a power line of TFT for driving the pixel. Another comprises a region of the LE layer formed on an electrode of capacitor connected to the TFTs to control the light-emitting element. Accordingly, without forming a flattening layer on the light-emitting layer, there is no electric short circuit between the lower electrode and the upper electrode.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: December 8, 2009
    Assignee: Hitachi Displays, Ltd.
    Inventors: Hajime Murakami, Yoshiro Mikami, Etsuko Nishimura, Shingo Ishihara, Masao Shimizu, Kenichi Onisawa
  • Publication number: 20090146930
    Abstract: Each TFT for driving each of a plurality of pixels arranged in a matrix-like configuration is configured using a stagger-type polycrystalline-Si TFT. A gate electrode, which is composed of a high-heat-resistant material capable of resisting high temperature at the time of polycrystalline-Si film formation, is disposed at a lower layer as compared with the polycrystalline-Si layer that forms a channel of each TFT. A gate line, which is composed of a low-resistance material, is disposed at an upper layer as compared with the polycrystalline-Si layer. The gate electrode and the gate line are connected to each other via a through-hole bored in a gate insulation film. Respective configuration components of each organic electro-luminescent element are partially co-used at the time of the line formation, thereby suppressing an increase in the steps, processes, and configuration components.
    Type: Application
    Filed: November 21, 2008
    Publication date: June 11, 2009
    Inventors: Etsuko NISHIMURA, Masatoshi Wakagi, Kenichi Onisawa, Mieko Matsumura
  • Publication number: 20080001544
    Abstract: The present invention provides OLEDs of the top emission type comprising organic light-emitting (LE) elements by preventing the problems such as the widening of the power lines, the reduction in the aperture ratio caused by the widening of the upper and the lower capacitor electrodes and the short circuit between the upper and the lower electrodes caused by the roughness of the flattening layers. Two kinds of the OLEDs are provided. One is an OLED comprising a region of LE layer sandwiched between the upper and lower electrodes is formed on a power line of TFT for driving the pixel. Another comprises a region of the LE layer formed on an electrode of capacitor connected to the TFTs to control the light-emitting element. Accordingly, without forming a flattening layer on the light-emitting layer, there is no electric short circuit between the lower electrode and the upper electrode.
    Type: Application
    Filed: March 29, 2007
    Publication date: January 3, 2008
    Applicant: HITACHI DISPLAYS, LTD.
    Inventors: Hajime MURAKAMI, Yoshiro MIKAMI, Etsuko NISHIMURA, Shingo ISHIHARA, Masao SHIMIZU, Kenichi ONISAWA
  • Patent number: 7211949
    Abstract: The present invention provides OLEDs of the top emission type comprising organic light-emitting (LE) elements by preventing the problems such as the widening of the power lines, the reduction in the aperture ratio caused by the widening of the upper and the lower capacitor electrodes and the short circuit between the upper and the lower electrodes caused by the roughness of the flattening layers. Two kinds of the OLEDs are provided. One is an OLED comprising a region of LE layer sandwiched between the upper and lower electrodes is formed on a power line of TFT for driving the pixel. Another comprises a region of the LE layer formed on an electrode of capacitor connected to the TFTs to control the light-emitting element. Accordingly, without forming a flattening layer on the light-emitting layer, there is no electric short circuit between the lower electrode and the upper electrode.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: May 1, 2007
    Assignee: Hitachi Displays, Ltd.
    Inventors: Hajime Murakami, Yoshiro Mikami, Etsuko Nishimura, Shingo Ishihara, Masao Shimizu, Kenichi Onisawa
  • Patent number: 7133218
    Abstract: Disclosed is an optical system that has superior optical characteristic and wear resistance and can be formed at low temperatures. An optical system 101 for adjusting visible light transmittance to have a desired value comprises fluoride 103, and at least part of the optical system has a crystal grain diameter of 3 nm to 10 nm. The fluoride 103 has a specific surface area of 1 m2/g to 5 m2/g.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: November 7, 2006
    Assignees: Shinmaywa Industries, Ltd., Hitachi, Ltd.
    Inventors: Takanobu Hori, Isao Tokomoto, Hiroshi Kajiyama, Akira Kato, Kenichi Onisawa, Makoto Abe, Shoichi Hirota, Tatsuya Sugita, Masaya Adachi, Katsumi Kondo
  • Publication number: 20060220582
    Abstract: The present invention provides OLEDs of the top emission type comprising organic light-emitting (LE) elements by preventing the problems such as the widening of the power lines, the reduction in the aperture ratio caused by the widening of the upper and the lower capacitor electrodes and the short circuit between the upper and the lower electrodes caused by the roughness of the flattening layers. Two kinds of the OLEDs are provided. One is an OLED comprising a region of LE layer sandwiched between the upper and lower electrodes is formed on a power line of TFT for driving the pixel. Another comprises a region of the LE layer formed on an electrode of capacitor connected to the TFTs to control the light-emitting element. Accordingly, without forming a flattening layer on the light-emitting layer, there is no electric short circuit between the lower electrode and the upper electrode.
    Type: Application
    Filed: May 23, 2006
    Publication date: October 5, 2006
    Inventors: Hajime Murakami, Yoshiro Mikami, Etsuko Nishimura, Shingo Ishihara, Masao Shimizu, Kenichi Onisawa
  • Patent number: 7067973
    Abstract: The present invention provides OLEDs of the top emission type comprising organic light-emitting (LE) elements by preventing the problems such as the widening of the power lines, the reduction in the aperture ratio caused by the widening of the upper and the lower capacitor electrodes and the short circuit between the upper and the lower electrodes caused by the roughness of the flattening layers. An OLED comprising a region of LE layer sandwiched between the upper and lower electrodes is formed on a power line of TFT for driving the pixel. Accordingly, without forming a flattening layer on the light-emitting layer, there is no electric short circuit between the lower electrode and the upper electrode.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: June 27, 2006
    Assignee: Hitachi Displays, Ltd.
    Inventors: Hajime Murakami, Yoshiro Mikami, Etsuko Nishimura, Shingo Ishihara, Masao Shimizu, Kenichi Onisawa
  • Publication number: 20050168142
    Abstract: The present invention provides OLEDs of the top emission type comprising organic light-emitting (LE) elements by preventing the problems such as the widening of the power lines, the reduction in the aperture ratio caused by the widening of the upper and the lower capacitor electrodes and the short circuit between the upper and the lower electrodes caused by the roughness of the flattening layers. Two kinds of the OLEDs are provided. One is an OLED comprising a region of LE layer sandwiched between the upper and lower electrodes is formed on a power line of TFT for driving the pixel. Another comprises a region of the LE layer formed on an electrode of capacitor connected to the TFTs to control the light-emitting element. Accordingly, without forming a flattening layer on the light-emitting layer, there is no electric short circuit between the lower electrode and the upper electrode.
    Type: Application
    Filed: March 25, 2005
    Publication date: August 4, 2005
    Inventors: Hajime Murakami, Yoshiro Mikami, Etsuko Nishimura, Shingo Ishihara, Masao Shimizu, Kenichi Onisawa
  • Patent number: 6882105
    Abstract: The present invention provides OLEDs of the top emission type comprising organic light-emitting (LE) elements by preventing the problems such as the widening of the power lines, the reduction in the aperture ratio caused by the widening of the upper and the lower capacitor electrodes and the short circuit between the upper and the lower electrodes caused by the roughness of the flattening layers. Two kinds of the OLEDs are provided. One is an OLED comprising a region of LE layer sandwiched between the upper and lower electrodes is formed on a power line of TFT for driving the pixel. Another comprises a region of the LE layer formed on an electrode of capacitor connected to the TFTs to control the light-emitting element. Accordingly, without forming a flattening layer on the light-emitting layer, there is no electric short circuit between the lower electrode and the upper electrode.
    Type: Grant
    Filed: September 2, 2003
    Date of Patent: April 19, 2005
    Assignee: Hitachi Displays, Ltd.
    Inventors: Hajime Murakami, Yoshiro Mikami, Etsuko Nishimura, Shingo Ishihara, Masao Shimizu, Kenichi Onisawa
  • Patent number: 6831413
    Abstract: A plasma display panel (PDP), consisting of a front panel (10) equipped with display electrodes (8) and a rear panel (4) equipped with address electrodes (3), that displays an image by causing discharge in a small discharge space formed between the two panels; wherein there are provided two layers of protective films (5, 6), made of metallic oxide, covering the dielectric layer (7) installed on the front panel (10); the outer, upper layer (6) being formed into a layer of material with a specific surface area of 20 m2/g or more and a film thickness of 1 &mgr;m or less, exhibiting a high discharge characteristic; and the inner, lower layer (5) being formed into a layer of material with a specific surface area of 10 m2/g or less and a film thickness of 1 &mgr;m or more, exhibiting a low water-adsorption characteristic.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: December 14, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Kajiyama, Akira Katou, Kenichi Onisawa, Tetsuro Minemura, Kazuo Uetani, Yasushi Ihara, Shiro Takigawa, Kouichi Nose, Isao Tokomoto, Yasuhiro Koizumi
  • Patent number: 6816134
    Abstract: There is provided a plasma display panel (PDP), consisting of a front panel (10) equipped with display electrodes (8) and a rear panel (4) equipped with address electrodes (3), that displays an image by causing discharge in a small discharge space formed between the two panels; wherein there are provided two layers of protective films (5, 6), made of metallic oxide, covering the dielectric layer (7) installed on the front panel (10); the outer, upper layer (6) being formed into a layer of material with a specific surface area of 20 m2/g or more and a film thickness of 1 &mgr;m or less, exhibiting a high discharge characteristic; and the inner, lower layer (5) being formed into a layer of material with a specific surface area of 10 m2/g or less and a film thickness of 1 &mgr;m or more, exhibiting a low water-adsorption characteristic.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: November 9, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Kajiyama, Akira Katou, Kenichi Onisawa, Tetsuro Minemura, Kazuo Uetani, Yasushi Ihara, Shiro Takigawa, Kouichi Nose, Isao Tokomoto, Yasuhiro Koizumi
  • Publication number: 20040113544
    Abstract: The present invention provides OLEDs of the top emission type comprising organic light-emitting (LE) elements by preventing the problems such as the widening of the power lines, the reduction in the aperture ratio caused by the widening of the upper and the lower capacitor electrodes and the short circuit between the upper and the lower electrodes caused by the roughness of the flattening layers. Two kinds of the OLEDs are provided. One is an OLED comprising a region of LE layer sandwiched between the upper and lower electrodes is formed on a power line of TFT for driving the pixel. Another comprises a region of the LE layer formed on an electrode of capacitor connected to the TFTs to control the light-emitting element. Accordingly, without forming a flattening layer on the light-emitting layer, there is no electric short circuit between the lower electrode and the upper electrode.
    Type: Application
    Filed: September 2, 2003
    Publication date: June 17, 2004
    Applicant: HITACHI DISPLAYS , LTD.
    Inventors: Hajime Murakami, Yoshiro Mikami, Etsuko Nishimura, Shingo Ishihara, Masao Shimizu, Kenichi Onisawa
  • Patent number: 6731364
    Abstract: A liquid crystal display device has image signal lines of a bottom gate type TFT, in which the image signal lines comprise a laminated film formed of a first conductive film disposed as a lower layer and a second conductive film disposed as an upper layer. The first conductive film is made of an alloy comprising Mo as a main ingredient and W, and the second conductive film is made of an alloy comprising Mo as a main ingredient and Zr. The device is capable of satisfying requirements of reduced resistance, improved dry etching resistance, selective wet etching with respect to the gate insulative film, the number of laminated layer of two or less, and tapered fabrication for the cross section.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: May 4, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Takuya Takahashi, Toshiki Kaneko, Katsumi Tamura, Kenichi Onisawa
  • Publication number: 20040061671
    Abstract: A display apparatus is arranged in a manner that each pixel includes a light emitting element for emitting light in response to a current flowing therein, a first switching element for fetching luminance information into a pixel from a signal line, and a second switching element for controlling a current amount to be supplied to the light emitting element in accordance with the luminance information thus fetched; the luminance information is fetched by fetching the signal voltage of the signal line when a scanning line connected to the pixel is selected; and the luminance information thus fetched in each of the pixels is kept in a capacitor even after the scanning line connected to the pixel is place in a non-selection state.
    Type: Application
    Filed: August 14, 2003
    Publication date: April 1, 2004
    Applicant: Hitachi Displays, Ltd.
    Inventors: Masahiro Kawasaki, Yoshirou Mikami, Hajime Murakami, Masahiko Andou, Kenichi Onisawa, Akitoyo Konno
  • Patent number: 6707512
    Abstract: A liquid crystal display unit having one pair of substrates, a liquid crystal layer held between the pair of substrates, a plurality of scanning lines formed on one of the pair of substrates, a plurality of data lines which cross the scanning lines in matrix form, thin film transistors formed near the crossing points of the scanning lines and data lines, and pixel electrodes connected to the thin film transistors. A source electrode and a drain electrode of each thin film transistor, and each data line, are made of a molybdenum alloy having a chromium content in a range of 1.5 weight % to 5 weight %.
    Type: Grant
    Filed: February 11, 2003
    Date of Patent: March 16, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Takuya Takahashi, Masahiro Ishii, Tsutomu Kasai, Tetsuya Kawamura, Katsumi Tamura, Toshiki Kaneko, Kenichi Onisawa
  • Patent number: 6674502
    Abstract: A liquid crystal display includes an insulative substrate having a surface treated with an oxygen plasma and a nitrogen-plasma-treated layer formed over said surface of said substrate. A surface of said nitrogen-plasma-treated layer has a nitrogen concentration of about 10 mol % or more.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: January 6, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Masatomo Terakado, Toshiki Kaneko, Takuya Takahashi, Kenichi Chahara, Kenichi Onisawa
  • Publication number: 20030147020
    Abstract: A liquid crystal display unit having one pair of substrates, a liquid crystal layer held between the pair of substrates, a plurality of scanning lines formed on one of the pair of substrates, a plurality of data lines which cross the scanning lines in matrix form, thin film transistors formed near the crossing points of the scanning lines and data lines, and pixel electrodes connected to the thin film transistors. A source electrode and a drain electrode of each thin film transistor, and each data line, are made of a molybdenum alloy having a chromium content in a range of 1.5 weight % to 5 weight %.
    Type: Application
    Filed: February 11, 2003
    Publication date: August 7, 2003
    Inventors: Takuya Takahashi, Masahiro Ishii, Tsutomu Kasai, Tetsuya Kawamura, Katsumi Tamura, Toshiki Kaneko, Kenichi Onisawa