Abstract: Provided is a nonvolatile storage device (200) capable of stably operating without increasing a size of a selection transistor included in each of memory cells. The nonvolatile storage device (200) includes: a semiconductor substrate (301) which has a P-type well (301a) of a first conductivity type; a memory cell array (202) which includes memory cells (M11) or the like each of which includes a variable resistance element (R11) and a transistor (N11) that are formed above the semiconductor substrate (301) and connected in series; and a substrate bias circuit (220) which applies, to the P-type well (301a), a bias voltage in a forward direction with respect to a source and a drain of the transistor (N11), when a voltage pulse for writing is applied to the variable resistance element (R11) included in the selected memory cell (M11) or the like.

Abstract: A nonvolatile memory apparatus and a nonvolatile data storage medium of the present invention, including nonvolatile memory elements each of which changes its resistance in response to electric pulses applied, comprises a first write circuit for performing first write in which a first electric pulse is applied to the nonvolatile memory element to switch a resistance value of the nonvolatile memory element from a first resistance value to a second resistance value and a second electric pulse which is opposite in polarity to the first electric pulse is applied to the nonvolatile memory element to switch the resistance value of the nonvolatile memory element from the second resistance value to the first resistance value.

Abstract: The variable resistance nonvolatile storage device reduces variations in a resistance value of a variable resistance element (100) in the low resistance state, performs stable operations, and includes an LR write circuit (500) (i) applying a voltage to a memory cell (102) so that a resistance state of the variable resistance element included in the memory cell is changed from high to low, and (ii) including a first driving circuit (510) and a second driving circuit (520) which apply voltages to the memory cell and which have connected output terminals. When applying a voltage to the memory cell, the first driving circuit supplies a first current, and the second driving circuit (i) supplies a second current when a voltage at the output terminal of the first driving circuit is higher than a reference voltage VREF, and (ii) is in a high impedance state when the voltage is lower than the VREF.

Abstract: To provide a variable resistance element writing method that, even when a variable resistance element has a possibility of becoming a half LR state, can ensure a maximum resistance change window by correcting the variable resistance element to a normal low resistance state.

Abstract: A writing method optimum for a variable resistance element which can maximize an operation window of the variable resistance element is provided. The writing method is performed for a variable resistance element that reversibly changes between a high resistance state and a low resistance state depending on a polarity of an applied voltage pulse. The writing method includes a preparation step (S50) and a writing step (S51, S51a, S51b). At the preparation step (S50), resistance values of the variable resistance element are measured by applying voltage pulses of voltages that are gradually increased to the variable resistance element, thereby determining the first voltage V1 for starting high resistance writing and the second voltage V2 having a maximum resistance value.

Abstract: Provided are a plurality of memory cell arrays 136 and 146 each having a plurality of nonvolatile memory elements having a characteristic whose resistance value changes according to electric pulses applied, and control units (102, 104, 108, 110, 114, 128, 130, 152) configured to write data to a memory cell array and to read data from another memory cell array such that writing of the data and reading of the data occur concurrently in writing of the data to the plurality of memory cell arrays.

Abstract: Provided is a nonvolatile storage device (200) capable of stably operating without increasing a size of a selection transistor included in each of memory cells. The nonvolatile storage device (200) includes: a semiconductor substrate (301) which has a P-type well (301a) of a first conductivity type; a memory cell array (202) which includes memory cells (M11) or the like each of which includes a variable resistance element (R11) and a transistor (N11) that are formed above the semiconductor substrate (301) and connected in series; and a substrate bias circuit (220) which applies, to the P-type well (301a), a bias voltage in a forward direction with respect to a source and a drain of the transistor (N11), when a voltage pulse for writing is applied to the variable resistance element (R11) included in the selected memory cell (M11) or the like.

Abstract: Provided are a plurality of memory cell arrays 136 and 146 each having a plurality of nonvolatile memory elements having a characteristic whose resistance value changes according to electric pulses applied, and control units (102, 104, 108, 110, 114, 128, 130, 152) configured to write data to a memory cell array and to read data from another memory cell array such that writing of the data and reading of the data occur concurrently in writing of the data to the plurality of memory cell arrays.

Abstract: [Objective] A nonvolatile memory apparatus and a nonvolatile data storage medium of the present invention, including nonvolatile memory elements each of which changes its resistance in response to electric pulses applied, comprises a first write circuit (106) for performing first write in which a first electric pulse is applied to the nonvolatile memory element to switch a resistance value of the nonvolatile memory element from a first resistance value to a second resistance value and a second electric pulse which is opposite in polarity to the first electric pulse is applied to the nonvolatile memory element to switch the resistance value of the nonvolatile memory element from the second resistance value to the first resistance value; and a second write circuit (108) for performing second write in which a third electric pulse is applied to the nonvolatile memory element to switch the resistance value of the nonvolatile memory element from a third resistance value to a fourth resistance value and a fourth ele

Abstract: A memory cell transistor array is composed of a plurality of memory cells having three or more threshold voltage distribution states in a single electric charge accumulation portion. A program sequence control circuit associates each piece of data included in a data set composed of a plurality of data values with any threshold voltage distribution of the three or more threshold voltage distributions, to store the data in the memory cell, and when rewriting the data stored in the memory cell, shifting threshold voltage distributions used for data storage in one direction to perform the data rewrite operation.

Abstract: In the circuit operation verifying method, initialization includes inputting circuit diagram data (a net list), specification information on respective circuit elements, and input data representing waveforms with time of voltages or currents used for operation simulation, and storing the circuit diagram data to memory. Operation of a semiconductor circuit to be verified is simulated using the circuit diagram data and the input data, and momentary voltage/current values at input terminals and the like of the circuit elements are stored in the memory. During the operation simulation, whether or not the circuit elements satisfy their voltage/current specifications and time specifications are concurrently verified based on the voltage/current values stored in the memory.

Abstract: A plurality of switches composing a voltage changing switch circuit 17 are supplied with a plurality of types of voltages, and are provided so as to correspond to a plurality of row decoders 2, such that each switch can separately select and output any of the plurality of types of voltages to the corresponding row decoder 2. Voltage boost circuits 7, 8 generate a plurality of types of voltages by boosting a power supply voltage. A regulator circuit 9 steps down at least one of the plurality of types of voltages generated by the voltage boost circuits 7, 8 to stabilize a voltage value, and outputs the resultant voltage to each switch. Each row decoder 2 selects a memory cell by using a voltage outputted from the corresponding switch. Thus, it is possible to reduce a time required for a program/program verify operation, while reducing power consumption.

Abstract: A plurality of switches composing a voltage changing switch circuit 17 are supplied with a plurality of types of voltages, and are provided so as to correspond to a plurality of row decoders 2, such that each switch can separately select and output any of the plurality of types of voltages to the corresponding row decoder 2. Voltage boost circuits 7, 8 generate a plurality of types of voltages by boosting a power supply voltage. A regulator circuit 9 steps down at least one of the plurality of types of voltages generated by the voltage boost circuits 7, 8 to stabilize a voltage value, and outputs the resultant voltage to each switch. Each row decoder 2 selects a memory cell by using a voltage outputted from the corresponding switch. Thus, it is possible to reduce a time required for a program/program verify operation, while reducing power consumption.

Abstract: The booster circuit includes a voltage reset circuit in a booster cell. The voltage reset circuit receives a gate voltage reset signal via a reset terminal of the booster circuit. The reset signal is asserted during abrupt change of the boosted voltage from high to low or during a restart after an instantaneous power interruption. The voltage reset circuit grounds the gate terminal of a charge-transfer transistor during the assertion of the gate voltage reset signal, to reset the gate potential of the charge-transfer transistor to the ground potential. By this resetting, normal boost operation is secured even in an event that a switching transistor remains cut-off because the amplitude of a boost clock signal is small due to use of low-voltage power supply.

Abstract: The booster circuit includes a voltage reset circuit in a booster cell. The voltage reset circuit receives a gate voltage reset signal via a reset terminal of the booster circuit. The reset signal is asserted during abrupt change of the boosted voltage from high to low or during a restart after an instantaneous power interruption. The voltage reset circuit grounds the gate terminal of a charge-transfer transistor during the assertion of the gate voltage reset signal, to reset the gate potential of the charge-transfer transistor to the ground potential. By this resetting, normal boost operation is secured even in an event that a switching transistor remains cut-off because the amplitude of a boost clock signal is small due to use of low-voltage power supply.

Abstract: In a circuit operation verifying method, initialization includes inputting circuit diagram data (a net list), specification information on respective circuit elements, and in-put data representing waveforms with time of voltages or currents used for operation simulation, and expanding the circuit diagram data to a memory. Operation of a semiconductor circuit to be verified is simulated using the circuit diagram data and the input data, and momentary volt-age/current values at input terminals and the like of the circuit elements are stored in the memory. During the operation simulation, whether or not the circuit elements satisfy their voltage/current specifications and time specifications are concurrently verified based on the voltage/current values stored in the memory.

Abstract: A test circuit for a semiconductor IC device for measuring a potential at an output node of a boost circuit included in the semiconductor IC device includes a switch having an end connected to the output node; a potential measurement terminal; and an n-channel MOS transistor including a gate connected to another end of the switch, a source connected to a reference voltage supply, and a drain connected to the potential measurement terminal.

Abstract: The present invention provides a semiconductor memory which can reduce the area of a circuit for replacing defective memory cells with redundant memory cells as well as reduce the time for writing defect information.

Abstract: In a charge pump circuit, the issues of increase in loss due to the backgating effect, increase in cost, risks of latch-up and charge leak and the like, which would be involved in achieving voltage reduction, are resolved with a simple circuit structure. A pump cell 31 has nMOS transistors M1-M3 and capacitors C1, C2. An auxiliary capacitor C is connected to an input node IN, and further p-well portions of the nMOS transistors M1-M3 are connected to this auxiliary capacitor C, the nMOS transistor M3 is interposed between each p-well portion and output node OUT, and the input node IN is connected to the gate of the nMOS transistor M3. Thus, with a simple circuit structure which involves only the use of the auxiliary capacitor C, voltage difference of the push-down of the p-well voltage is increased so that the deterioration of pump efficiency due to the backgating effect in the voltage reduction of power supply voltage is eliminated and that latch-up and charge leak are prevented.