Abstract: A data processor that executes arithmetic operations between first and second binary numbers, stored in different registers, of different lengths, with the first number having a byte-length smaller than the register, and the second number having a byte-length equal to the register, by storing the first number so that its lower order bit is justified with the lower order bit of the second number. Additionally, data having different bit and byte polarities are processed by reversing the bit and byte order of the data as required.

Abstract: A data processor in accordance with the present invention can normally operate bit-string data while avoiding a breakage of the data even in the case where a read-out area of the bit string and a write-in area thereof are overlapped by each other by providing an operation code of an instruction with an option designating the direction of bit processing.

Abstract: A method for searching the memory of a data processing apparatus including a decoder for decoding the contents of an instruction and an execution unit for executing the instruction based on an output from the decoder is performed in response to a search instruction which identifies a desired data storage area from a plurality of data storage areas in the memory which includes an array data structure.

Abstract: A data processor which has instructions of operation and comparison when including the signed binary number represented by complement on 2 as the object and has a flag correctly representing the result of the operation as positive or negative regardless of whether or not overflow occurs so as to correlate the arithmetic operation close with a status flag change, thereby facilitating mathematical interpretation of the result of the operation.

Abstract: A data processor in accordance with the present invention can normally operate bit-string data while avoiding a breakage of the data even in the case where a read-out area of the bit string and a write-in area thereof are overlapped each other by providing an operation code of an instruction with an option designating the direction of bit processing.

Abstract: A device for detecting whether addresses used for accessing in a memory mapped I/O system are present in the I/O area or not is provided. The device includes a mask register for logically ANDing with an incoming address. The output of the ANDing process is exclusive-ORed with an I/O address register. When an operand fetch is made to an I/O area the fetch is suspended during execution of preceding instructions. When the instruction fetch unit seeks an I/O area address, or the address calculation unit seeks an I/O area address, or data is fetched across a boundary of the I/O area, an exception is activated.

Abstract: In addition to an ordinary bit field instruction without limitation which makes use of an offset value and a field width, a bit field instruction with limitation which does not calculate the spread of the bit field is separately installed. In the present invention the calculation for determination of the spread of the bit field is not performed when the bit field instruction with limitation is executed. In addition, when executing a bit field instruction with limitation, the offset value and the field width can be obtained directly as immediate values thereby decreasing the execution time of the instruction.

Abstract: A method for searching the memory of a data processing apparatus including a decoder for decoding the contents of an instruction and an execution unit for executing the instruction based on an output from the decoder is performed in response to a search instruction which identifies a desired data storage area from a plurality of data storage areas in the memory which includes an array data structure.

Abstract: A data processing system includes three resources, i.e., a memory, a general purpose register file having a plurality of elements and a stack having a top. The system further includes a first mechanism for making the top of the stack correspond to at least one of the elements in the general purpose register and a second mechanism for controlling the operation of the stack. When the element to which the top of the stack corresponds is specified in an instruction register of the system, the top of the stack is selected to be accessed by the first mechanism and the operation of the stack is controlled by the second mechanism.