Patents by Inventor Ken Shibata
Ken Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11965817Abstract: Disclosed is a cell classification method, to be executed by an analyzer, for classifying cells contained in a specimen, including: preparing a first measurement sample by treating a specimen under a first preparation condition; obtaining a first signal from the prepared first measurement sample; classifying, by using the first signal, cells contained in the first measurement sample; preparing a second measurement sample by treating the specimen under a second preparation condition different from the first preparation condition; obtaining a second signal from the prepared second measurement sample; classifying, by using the second signal, cells contained in the second measurement sample; and comparing a result of the cell classification performed by using the first signal and a result of the cell classification performed by using the second signal, with each other, and outputting an analysis result including a number of cells on the basis of a result of the comparison.Type: GrantFiled: March 4, 2021Date of Patent: April 23, 2024Assignee: SYSMEX CORPORATIONInventors: Yuki Shida, Yukiko Nakamura, Ken Nishikawa, Kota Misawa, Hikaru Onoue, Takaaki Nagai, Masaki Abe, Takahito Mihara, Masaharu Shibata, Konobu Kimura
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Patent number: 11938980Abstract: A RIO device mounted to a train includes an output unit that outputs a signal to a relay mounted to the train, and a controller that controls whether or not to cause the output unit to output the signal. The output unit includes a readback circuit that detects whether or not the signal is outputted from the output unit. The controller makes a signal stop request and a signal output request to the output unit before operation of the train starts, acquires a detection result of the readback circuit while each of the signal stop request and the signal output request is performed, and detects abnormality of the output unit using the detection result.Type: GrantFiled: January 16, 2018Date of Patent: March 26, 2024Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Ken Shibata, Tetsuo Komura, Hiromi Goda, Hiroshi Jota, Kentaro Hoshino
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Publication number: 20230406376Abstract: A central apparatus to be installed on a train, includes: a communication unit that acquires device information indicating a state of a device from the device installed on the train; and a control unit that determines whether to change a failure level to be displayed, with reference to a failure level display definition on the basis of the device information acquired from the device, the failure level display definition defining a condition for changing the failure level indicating a state of a failure of the device to be displayed when the failure of the device is displayed on a display apparatus.Type: ApplicationFiled: September 14, 2020Publication date: December 21, 2023Applicant: Mitsubishi Electric corporationInventors: Kiyomasa MIWA, Takahiro ITO, Ken SHIBATA
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Publication number: 20210061325Abstract: A RIO device mounted to a train includes an output unit that outputs a signal to a relay mounted to the train, and a controller that controls whether or not to cause the output unit to output the signal. The output unit includes a readback circuit that detects whether or not the signal is outputted from the output unit. The controller makes a signal stop request and a signal output request to the output unit before operation of the train starts, acquires a detection result of the readback circuit while each of the signal stop request and the signal output request is performed, and detects abnormality of the output unit using the detection result.Type: ApplicationFiled: January 16, 2018Publication date: March 4, 2021Applicant: Mitsubishi Electric CorporationInventors: Ken SHIBATA, Tetsuo Komura, Hiromi GODA, Hiroshi JOTA, Kentaro Hoshino
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Patent number: 10566047Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.Type: GrantFiled: January 17, 2019Date of Patent: February 18, 2020Assignee: Renesas Electronics CorporationInventors: Kiyotada Funane, Ken Shibata, Yasuhisa Shimazaki
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Patent number: 10510400Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.Type: GrantFiled: April 19, 2018Date of Patent: December 17, 2019Assignee: Renesas Electronics CorporationInventors: Toshiaki Sano, Ken Shibata, Shinji Tanaka, Makoto Yabuuchi, Noriaki Maeda
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Publication number: 20190147940Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.Type: ApplicationFiled: January 17, 2019Publication date: May 16, 2019Inventors: Kiyotada FUNANE, Ken SHIBATA, Yasuhisa SHIMAZAKI
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Patent number: 10224095Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.Type: GrantFiled: October 27, 2017Date of Patent: March 5, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kiyotada Funane, Ken Shibata, Yasuhisa Shimazaki
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Publication number: 20180240513Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.Type: ApplicationFiled: April 19, 2018Publication date: August 23, 2018Inventors: Toshiaki SANO, Ken SHIBATA, Shinji TANAKA, Makoto YABUUCHI, Noriaki MAEDA
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Patent number: 9978445Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.Type: GrantFiled: December 9, 2016Date of Patent: May 22, 2018Assignee: Renesas Electronics CorporationInventors: Toshiaki Sano, Ken Shibata, Shinji Tanaka, Makoto Yabuuchi, Noriaki Maeda
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Publication number: 20180069010Abstract: A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP2) for the plurality of wells PW is arranged on one side so as to interpose the AR1 in a Y-axis direction, and a common power feeding region (ARN2) for the plurality of wells NW is arranged on the other side. In the power feeding region (ARP2) for the PW wells, a p+-type power-feeding diffusion layer P+ (DFW) having an elongate shape extending in the X-axis direction is formed. A plurality of gate layers GT extending in the X-axis direction to cross the boundary between the PW and NW wells are arranged in the AR1, and a plurality of MIS transistors are correspondingly formed.Type: ApplicationFiled: October 27, 2017Publication date: March 8, 2018Inventors: Ken SHIBATA, Yuta YANAGITANI
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Publication number: 20180068710Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.Type: ApplicationFiled: October 27, 2017Publication date: March 8, 2018Inventors: Kiyotada FUNANE, Ken SHIBATA, Yasuhisa SHIMAZAKI
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Patent number: 9865604Abstract: A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP2) for the plurality of wells PW is arranged on one side so as to interpose the AR1 in a Y-axis direction, and a common power feeding region (ARN2) for the plurality of wells NW is arranged on the other side. In the power feeding region (ARP2) for the PW wells, a p+-type power-feeding diffusion layer P+(DFW) having an elongate shape extending in the X-axis direction is formed. A plurality of gate layers GT extending in the X-axis direction to cross the boundary between the PW and NW wells are arranged in the AR1, and a plurality of MIS transistors are correspondingly formed.Type: GrantFiled: September 27, 2016Date of Patent: January 9, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Ken Shibata, Yuta Yanagitani
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Patent number: 9830975Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.Type: GrantFiled: May 1, 2017Date of Patent: November 28, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kiyotada Funane, Ken Shibata, Yasuhisa Shimazaki
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Publication number: 20170236576Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.Type: ApplicationFiled: May 1, 2017Publication date: August 17, 2017Inventors: Kiyotada FUNANE, Ken SHIBATA, Yasuhisa SHIMAZAKI
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Patent number: 9672872Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.Type: GrantFiled: June 23, 2016Date of Patent: June 6, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kiyotada Funane, Ken Shibata, Yasuhisa Shimazaki
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Publication number: 20170092352Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.Type: ApplicationFiled: December 9, 2016Publication date: March 30, 2017Inventors: Toshiaki SANO, Ken SHIBATA, Shinji TANAKA, Makoto YABUUCHI, Noriaki MAEDA
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Publication number: 20170018554Abstract: A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP2) for the plurality of wells PW is arranged on one side so as to interpose the AR1 in a Y-axis direction, and a common power feeding region (ARN2) for the plurality of wells NW is arranged on the other side. In the power feeding region (ARP2) for the PW wells, a p+-type power-feeding diffusion layer P+(DFW) having an elongate shape extending in the X-axis direction is formed. A plurality of gate layers GT extending in the X-axis direction to cross the boundary between the PW and NW wells are arranged in the AR1, and a plurality of MIS transistors are correspondingly formed.Type: ApplicationFiled: September 27, 2016Publication date: January 19, 2017Inventors: Ken SHIBATA, Yuta YANAGITANI
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Patent number: 9548106Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.Type: GrantFiled: April 21, 2016Date of Patent: January 17, 2017Assignee: Renesas Electronics CorporationInventors: Toshiaki Sano, Ken Shibata, Shinji Tanaka, Makoto Yabuuchi, Noriaki Maeda
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Patent number: 9478554Abstract: A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP2) for the plurality of wells PW is arranged on one side so as to interpose the AR1 in a Y-axis direction, and a common power feeding region (ARN2) for the plurality of wells NW is arranged on the other side. In the power feeding region (ARP2) for the PW wells, a p+-type power-feeding diffusion layer P+(DFW) having an elongate shape extending in the X-axis direction is formed. A plurality of gate layers GT extending in the X-axis direction to cross the boundary between the PW and NW wells are arranged in the AR1, and a plurality of MIS transistors are correspondingly formed.Type: GrantFiled: January 7, 2016Date of Patent: October 25, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Ken Shibata, Yuta Yanagitani