Patents by Inventor Ken Shibata
Ken Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8189358Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC is disposed in a matrix shape, each word line is disposed in the order like WLA0, WLB0, WLB1, WLA1, WLA2, . . . . Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line as a criterion, while the word lines of different ports are disposed at the pitch d1 on the other. With the above configuration, for example, as compared with a case of alternately disposing WLA and WLB, interference between ports can be reduced even with a small area, and the noise margin can be expanded.Type: GrantFiled: April 6, 2011Date of Patent: May 29, 2012Assignee: Renesas Electronics CorporationInventors: Kiyotada Funane, Ken Shibata, Yasuhisa Shimazaki
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Publication number: 20120069692Abstract: A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.Type: ApplicationFiled: September 21, 2011Publication date: March 22, 2012Inventors: BINHAKU TARUISHI, HIROKI MIYASHITA, KEN SHIBATA, MASASHI HORIGUCHI
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Patent number: 8031546Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.Type: GrantFiled: February 23, 2010Date of Patent: October 4, 2011Assignees: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd.Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Publication number: 20110182100Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC is disposed in a matrix shape, each word line is disposed in the order like WLA0, WLB0, WLB1, WLA1, WLA2, . . . . Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line as a criterion, while the word lines of different ports are disposed at the pitch d1 on the other. With the above configuration, for example, as compared with a case of alternately disposing WLA and WLB, interference between ports can be reduced even with a small area, and the noise margin can be expanded.Type: ApplicationFiled: April 6, 2011Publication date: July 28, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Kiyotada FUNANE, Ken SHIBATA, Yasuhisa SHIMAZAKI
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Patent number: 7940542Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC is disposed in a matrix shape, each word line is disposed in the order like WLA0, WLB0, WLB1, WLA1, WLA2, . . . . Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line as a criterion, while the word lines of different ports are disposed at the pitch d1 on the other. With the above configuration, for example, as compared with a case of alternately disposing WLA and WLB, interference between ports can be reduced even with a small area, and the noise margin can be expanded.Type: GrantFiled: June 23, 2008Date of Patent: May 10, 2011Assignee: Renesas Electronics CorporationInventors: Kiyotada Funane, Ken Shibata, Yasuhisa Shimazaki
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Publication number: 20100149883Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.Type: ApplicationFiled: February 23, 2010Publication date: June 17, 2010Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Patent number: 7693000Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example; which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.Type: GrantFiled: October 15, 2008Date of Patent: April 6, 2010Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., LtdInventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Publication number: 20090059640Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC is disposed in a matrix shape, each word line is disposed in the order like WLA0, WLB0, WLB1, WLA1, WLA2, . . . . Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line as a criterion, while the word lines of different ports are disposed at the pitch d1 on the other. With the above configuration, for example, as compared with a case of alternately disposing WLA and WLB, interference between ports can be reduced even with a small area, and the noise margin can be expanded.Type: ApplicationFiled: June 23, 2008Publication date: March 5, 2009Inventors: Kiyotada Funane, Ken Shibata, Yasuhisa Shimazaki
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Publication number: 20090046517Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example; which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.Type: ApplicationFiled: October 15, 2008Publication date: February 19, 2009Inventors: Binhaku TARUISHI, Hiroki MIYASHITA, Ken SHIBATA, Masashi HORIGUCHI
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Patent number: 7453738Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example; which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.Type: GrantFiled: July 6, 2005Date of Patent: November 18, 2008Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd.Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Publication number: 20050243644Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example; which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.Type: ApplicationFiled: July 6, 2005Publication date: November 3, 2005Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Patent number: 6954384Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.Type: GrantFiled: July 5, 2002Date of Patent: October 11, 2005Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd.Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Publication number: 20020163846Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instructions for the memory unit is provided, the data input buffer is rendered active in advance before the instructions for the write operation is provided, whereby wastefully consumed power is reduced.Type: ApplicationFiled: July 5, 2002Publication date: November 7, 2002Applicant: Hitachi, Ltd.Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Patent number: 6424590Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instructions for the memory unit is provided, the data input buffer is rendered active in advance before the instructions for the write operation is provided, whereby wastefully consumed power is reduced.Type: GrantFiled: December 21, 2001Date of Patent: July 23, 2002Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Publication number: 20020054516Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instructions for the memory unit is provided, the data input buffer is rendered active in advance before the instructions for the write operation is provided, whereby wastefully consumed power is reduced.Type: ApplicationFiled: December 21, 2001Publication date: May 9, 2002Applicant: Hitachi, Ltd.Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Patent number: 6339552Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.Type: GrantFiled: August 18, 2000Date of Patent: January 15, 2002Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Patent number: 5880531Abstract: A semiconductor memory device having inner lead portions of a plurality of leads disposed through at least one insulating film on a semiconductor chip and electrically insulated from the semiconductor chip, includes bonding pads for at least data input/output arranged in two rows axially symmetrically in a substantially central portion of the semiconductor chip interposed between memory arrays and bonding wires for connecting the inner lead portions and the bonding pads.Type: GrantFiled: November 19, 1997Date of Patent: March 9, 1999Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Kouki Hagiya, Ken Shibata
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Patent number: 5835020Abstract: A multiple communication system used in an automobile includes miniaturized multi-function electric units. Each electric unit is composed of a CPU and a bus driver, and the CPU is connected to a bus line through the bus driver. The CPU of each of the electric units includes a communication processing program, and communication can be carried out among the electric units through the bus line using the communication processing program. Each CPU can be connected to its associated bus driver through only two data I/O ports. Thus, the number of I/O data ports is reduced as compared with the case in which conventional communication ICs are used. Further, since the bus drivers of small size are used, the electric units can be miniaturized. Further, the communication processing program of each CPU can be rewritten through the bus line.Type: GrantFiled: July 1, 1996Date of Patent: November 10, 1998Assignee: Alps Electric Co., LtdInventors: Ken Mizuta, Ken Shibata, Yukio Miura
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Patent number: 5754838Abstract: In a synchronous DRAM, internal clock signals in synchronism with clock signals fed from an external unit are generated by a PLL circuit or a DLL circuit to eliminate signal delays. In order to provide a dynamic RAM that is capable of stably operating with clock signals over a wide range of frequencies; a change-over circuit is provided which changes the range of variable frequencies of the PLL circuit or changes the variable delay time of the DLL circuit based upon mode-setting information fed from an external unit.Type: GrantFiled: December 21, 1995Date of Patent: May 19, 1998Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Ken Shibata, Kanji Oishi
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Patent number: 5473198Abstract: A semiconductor memory device having inner lead portions of a plurality of leads disposed through at least one insulating film on a semiconductor chip and electrically insulated from the semiconductor chip, includes bonding pads for at least data input/output arranged in two rows axially symmetrically in a substantially central portion of the semiconductor chip interposed between memory arrays and bonding wires for connecting the inner lead portions and the bonding pads.Type: GrantFiled: June 10, 1994Date of Patent: December 5, 1995Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Kouki Hagiya, Ken Shibata