Patents by Inventor Kendell A. Chilton

Kendell A. Chilton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9946471
    Abstract: The wear of storage devices in a storage array or storage server cluster is unleveled via modal Read/Write to create a plurality of endurance sets, each endurance set having devices with statistically similar amount of wear in a given period of time, and different endurance sets are subjected to different amounts of wear over a given period of time. The storage devices are organized into RAID groups such that multiple devices associated with the same RAID group are not members of the same endurance set. The number of devices in each endurance set may be selected to match the number of spare failover storage devices.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: April 17, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Sachin More, Kendell Chilton, Barry A. Burke
  • Patent number: 9652352
    Abstract: Described are techniques for reconfiguring a storage device. A first plurality of parameters characterizing the storage device at a first point in time are received. The first plurality of parameters includes a first raw capacity and a first published capacity. The first raw capacity represents a physical storage capacity of the storage device. The first published capacity represents a logical storage capacity of the storage device. A second plurality of parameters is determined characterizing the storage device at a subsequent second point in time. The second plurality of parameters includes a second raw capacity and a second published capacity, The storage device is used at the first point in time as a device having the first plurality of parameters and at the second point in time as a device having the second plurality of parameters.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: May 16, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Kendell Chilton, Sachin More
  • Patent number: 8838887
    Abstract: Delivering different data response time performance from a plurality of disk drives having similar performance characteristics includes subdividing each disk drive platter of the disk drives into at least two separate portions, where a first portion has a first average response time and the second portion has a second average response time that is greater than the first average response time and includes placing data that is relatively frequently accessed in the first portion of the disk platters of the disk drives to provide a subset of data having a relatively higher data response time performance than other data. Data having a relatively lower data response time performance may be placed on disk drives containing data having a relatively higher data response time performance.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: September 16, 2014
    Assignee: EMC Corporation
    Inventors: Barry Burke, Kendell Chilton, Sachin More
  • Patent number: 8554943
    Abstract: A method and structure for detecting whether the packets received by the switch are low latency packets or high bandwidth packets and routing detected low latency packets to a first one of a pair of switching structures and for high bandwidth packets to a second one of the pair of switching structures. The switch includes an output section for detecting whether a low latency packet is being received during transmission of a high bandwidth packet and, under such detected condition interrupting the transmission of the high bandwidth packet, transmitting the low latency packet, and then transmitting a remaining portion of the high bandwidth packet. The switch inserts delimiters at the start of transmission of the low latency packet and an end of transmission of the low latency packet. The transmission of the low latency packet commences immediately upon detection of such low latency packet.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: October 8, 2013
    Assignee: EMC Corporation
    Inventors: John K. Walton, Kendell Chilton
  • Patent number: 8375187
    Abstract: In a data storage system, a controller schedules I/Os to storage devices so that each one substantially performs only reads or only writes, thereby increasing performance. At least one storage device is designated as a current write device. The remainder of the devices are designated current read devices. Host write data is stored in a buffer memory. Storage device reads occur only from the current read devices. Storage device writes occur only to the current write device(s). In response to a triggering event, the designations are updated so that a different storage device is designated the current write device, and the remainder of the storage devices are designated the current read devices. A triggering event may include but not be limited to a time period, number of writes, cache size, device wear, environmental conditions, application requirements, or combination.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: February 12, 2013
    Assignee: EMC Corporation
    Inventors: Kendell Chilton, Sachin More
  • Patent number: 8010738
    Abstract: Described are techniques for processing requests for a device. One embodiment is directed to a method including receiving a first value indicating an expected usage of said device prior to failure of said device, receiving a second value indicated a specified lifetime of said device, said second value being in units of time, determining a target rate of usage for the device in accordance with said first value and said second value, determining a current rate of usage for the device, determining whether the current rate of usage is greater than the target rate of usage; and, if said current rate of usage is greater than the target rate of usage, performing an action to reduce the current rate of usage for the device.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: August 30, 2011
    Assignee: EMC Corporation
    Inventors: Kendell A. Chilton, Sachin More
  • Patent number: 7865761
    Abstract: A data storage apparatus (e.g., a flash memory appliance) includes a set of memory modules, an interface and a main controller coupled to the each memory module and to the interface. Each memory module has non-volatile semiconductor memory (e.g., flash memory). The interface is arranged to communicate with a set of external devices. The main controller is arranged to (i) store data within and (ii) retrieve data from the non-volatile semiconductor memory of the set of memory modules in an uneven manner on behalf of the set of external devices to unevenly wear out the memory modules over time. Due to the ability of the data storage apparatus to utilize each memory module through its maximum life and to stagger the failures of the modules, such a data storage apparatus is well-suited as a high availability storage device, e.g., a semiconductor cache for a fault tolerant data storage system.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: January 4, 2011
    Assignee: EMC Corporation
    Inventor: Kendell Chilton
  • Patent number: 7821922
    Abstract: A packet switching network having a plurality of nodes and a network having: a plurality of switches couples to the nodes and links interconnecting ports of the plurality of switches. Each one of the switches has a normal routing table for routing packets from a source one of the nodes to a destination one of the nodes through the network in according to the normal routing table and, for, upon such upon such source one of the nodes detecting a fault in transmission of such packet, routing such to a predetermined designated fault one of the ports of such switch.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: October 26, 2010
    Assignee: EMC Corporation
    Inventors: John K. Walton, Kendell Chilton, James Guyer
  • Patent number: 7712004
    Abstract: An error checking system includes an input device for receiving a data element including parity information; a parity check device for checking the parity information of the data element to determine whether the data element is valid; a CRC generator coupled to the parity check device for generating a CRC for the data element; and an output device for transmitting the data element with the parity information and CRC to a downstream device over a transmission link. The parity check device is operative to output a corruption signal to the CRC generator if the parity check device determines that the data element is invalid, to instruct the CRC generator to corrupt the CRC generation for that data element.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: May 4, 2010
    Assignee: EMC Corporation
    Inventors: Brian K. Campbell, Kendell A. Chilton, Christopher S. MacLellan, Ofer Porat
  • Patent number: 7552282
    Abstract: Described are techniques for selective data replication. Cached data is replicated if it is characterized as critical. Critical data may include data associated with a write I/O operation. Cache locations are selected for replicated data so that a first location is mapped to a first memory board and a second location is mapped to a second memory board. Data for a read operation is not replicated in cache. Other non-cache data that is critical and thus replicated includes metadata. Cache locations for data of read and write I/O operations are selected dynamically at the time the I/O operation is made from the same pool of cache locations.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: June 23, 2009
    Assignee: EMC Corporation
    Inventors: Michael Bermingham, Kendell A. Chilton, Robert DeCrescenzo, Mark J. Halstead, Haim Kopylovitz, Steven T. McClure, James M. McGillis, Ofer E. Michael, Brett D. Niver, John K. Walton
  • Patent number: 7454536
    Abstract: A queuing system wherein at least one input/output (I/O) interface having an outbound queue. A plurality of processing units is coupled to the at least one I/O interface. Each one of the processing units is coupled to a corresponding processing unit memory. Each one of the processing unit memories has an inbound queue for such coupled processing unit. The at least one I/O interface outbound queue stores outbound information being returned to the I/O interface after being processed by one of the processing units. The I/O interface creates queue indices for storage in the inbound queues of the processor unit memories. The I/O interface includes a translation table, such table storing at a location a producer index for the plurality of processing units and a consumer index for such plurality of processing units.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: November 18, 2008
    Assignee: EMC Corporation
    Inventors: John K. Walton, William F. Baxter, III, Kendell A. Chilton, Daniel Castel, Michael Bermingham, James M. Guyer
  • Patent number: 7437425
    Abstract: A system interface having a plurality of directors, one portion of such directors being adapted for coupling to a host computer/server and another portion of the directors being adapted for coupling to a bank of disk drives. The plurality of directors are interconnected through a network. A common resource section is provided having a resource shared among the plurality of directors. The common shared resource section includes a shared computer code used by the plurality of directors. The code includes computer code for booting up each one of the plurality directors. The common shared code storage section is interconnected to the directors through the network. A second, redundant common shared resource section is provided. The network is a packet switching network.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: October 14, 2008
    Assignee: EMC Corporation
    Inventors: John K. Walton, William F. Baxter, III, Kendell A. Chilton, Daniel Castel, Michael Bermingham, James M. Guyer
  • Patent number: 7272668
    Abstract: A system having a plurality of printed circuit broads each one having an electrical component thereon. A backplane carries a signal indicative of a performance characteristic of the electrical components on the plurality of printed circuit boards plugged into such backplane. The performance characteristic may be, for example component speed, operating protocol, etc. System start-up is interrupted upon detection of such incompatibility. After start up, upon plugging an additional printed circuit broad having an electrical component thereon with an operating incompatible with the electrical components on the plurality of printed circuit boards into the backplane, the electrical component on such additional printed circuit will not be electrically coupled to the electrical component on the additional printed circuit board from the electrical components of the plurality of printed circuit boards.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: September 18, 2007
    Assignee: EMC Corporation
    Inventors: John K. Walton, Ofer Porat, Christopher S. MacLellan, Daniel Castel, Kendell A. Chilton, Brian K. Campbell, Gregory S. Robidoux, Brian D. Magnuson
  • Patent number: 7234021
    Abstract: A data storage system has disk drives, memory circuit boards to store a set of hash lists and a cache, and a front-end interface. The front-end interface is configured to receive a data element request including a disk address identifying a set of disk drive locations that stores the data element; perform a hash function on the disk address in order to generate a hash pointer; and provide a search command, the disk address and the generated hash pointer to the memory circuit boards. The memory circuit boards are configured to receive the search command, the disk address, and the hash pointer from the front-end interface; search the set of hash lists based on the hash pointer and the disk address; and provide an indication to the front-end interface indicating whether the set of hash lists includes an entry indicating that the data element resides in cache.
    Type: Grant
    Filed: October 8, 2001
    Date of Patent: June 19, 2007
    Assignee: EMC Corporation
    Inventor: Kendell A. Chilton
  • Patent number: 7124245
    Abstract: A system interface having: a plurality of front end directors adapted for coupling to a host computer/server; a plurality of back end directors adapted for coupling to a bank of disk drives; a data transfer section having cache memory; a cache memory manager; and, a message network. The cache memory is coupled to the plurality of front end and back end directors. The messaging network operates independently of the data transfer section and is coupled to the plurality of front end and back end. The front end and back end directors control data transfer between the host computer/server and the bank of disk drives in response to messages passing between the front end directors and the back end directors through the messaging network to facilitate data transfer between host computer/server and the bank of disk drives. The data passes through the cache memory in the data transfer section as such data passes between the host computer and the bank of disk drives.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: October 17, 2006
    Assignee: EMC Corporation
    Inventors: John K. Walton, William F. Baxter, III, Kendell A. Chilton, Daniel Castel, Michael Bermingham, James M. Guyer
  • Patent number: 7117305
    Abstract: A system interface having: a plurality of front end directors adapted for coupling to a host computer/server; a plurality of back end directors adapted for coupling to a bank of disk drives; a data transfer section having cache memory; a cache memory manager; and, a message network. The cache memory is coupled to the plurality of front end and back end directors. The messaging network operates independently of the data transfer section and is coupled to the plurality of front end and back end. The front end and back end directors control data transfer between the host computer/server and the bank of disk drives in response to messages passing between the front end directors and the back end directors through the messaging network to facilitate data transfer between host computer/server and the bank of disk drives. The data passes through the cache memory in the data transfer section as such data passes between the host computer and the bank of disk drives.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: October 3, 2006
    Assignee: EMC Corporation
    Inventor: Kendell A. Chilton
  • Patent number: 7076636
    Abstract: A data storage system includes a set of storage devices, a memory circuit board that includes a cache to temporarily store copies of data elements stored in the set of storage devices, and a processor circuit board that operates as at least one of a front-end interface between an external device and the cache and a back-end interface between the cache and the set of storage devices. The memory circuit board is configured to receive, from the processor circuit board, a communication that includes a script command and a payload. The payload includes a series of individual instructions. The memory circuit board is further configured to parse the payload to identify the series of individual instructions in response to the script command, and to perform a series of operations in accordance with the identified series of individual instructions.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: July 11, 2006
    Assignee: EMC Corporation
    Inventor: Kendell A. Chilton
  • Patent number: 7073024
    Abstract: A method for storing data on a disk drive and checking the validity of data read from such disk drive. The method includes: transmitting the data from a source thereof for storage in the disk drive through a first transmission path and transmitting a CRC together with parity associated with such data for storage in a storage medium through a second path separate from the disk drive. The data stored on the disk drive is retrieved. A CRC associated with the retrieved data is determined. The determined CRC and the CRC stored in the storage medium are compared. With such method, if data and ins associated CRC are written into the incorrect location in the disk drive, during a read an error will be detected because the CRC of the read data will not match the CRC associated with the read data stored on the storage medium.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: July 4, 2006
    Assignee: EMC Corporation
    Inventor: Kendell A. Chilton
  • Patent number: 7027439
    Abstract: A data storage system has a backplane, processing circuitry and a NIC. The processing circuitry is physically connected to the backplane, and can perform block-based data access operations. The NIC has a first port that that couples to an external network, a second port that physically connects to the backplane, and control circuitry interconnected between the first port and the second port.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: April 11, 2006
    Assignee: EMC Corporation
    Inventors: Jonathan J. Barrow, Kendell A. Chilton
  • Patent number: 7023869
    Abstract: A network adapter is provided that may be used in a network data storage system to facilitate data communication among external data exchanging devices and an input/output (I/O) controller residing in the system. The adapter includes one or more interfaces that may be coupled to an electrical backplane in the system. The backplane is coupled to the controller, and is configured to permit communication between the controller and the adapter when the interfaces are coupled to the backplane. The adapter may provide one or more file server-like behaviors.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: April 4, 2006
    Assignee: EMC Corporation
    Inventors: Jonathan J. Barrow, Kendell A. Chilton